This is an old revision of the document!
EE6324: Phase-Locked Loops(May-Aug. 2020)
Instructor
Classroom
Schedule
Tue./Thu.: 4:00-5:15 PM
Alternate Friday
Course page on moodle
Registered students can login and see the course page at https://courses.iitm.ac.in/. Resources, tutorials, exam schedules, discussion forum etc. can be accessed from the moodle page.
Teaching Assistants
Evaluation
Assignments (10%)
Quiz-I (20%)
Quiz-II (20%)
Project (20%)
End Sem (30%)
Recorded lectures
The recorded lectures are listed below.
-
Lecture#2(
pdf): Crystal/LC oscillator as clock source, Basic operation of a PLL
Lecture#3(
pdf): Basic operation of a PLL with mixer, loop filter, and voltage controlled oscillator at block level
Lecture#4(
pdf): Basic operation of a PLL with mixer, loop filter, and voltage controlled oscillator at block level (contd.)
Lecture#5(
pdf): Small-signal model of a basic PLL, Type/order of a PLL
-
-
Lecture#8(
pdf): Frequency acquisition in Type-I/II PLL (contd.)
Lecture#9(
pdf): Frequency acquisition in Type-II PLL (contd.)
-
-
Lecture#12(
pdf): XOR based PD, S-R flip flop based PD, Range extension of PDs
-
-
-
Lecture#16(
pdf): Design methodology for a type-II order-3 charge-pump PLL (CP-PLL)
Lecture#17(
pdf): Sources of non-linearity in CP-PLL, Noise analysis in CP-PLLs
-
-
-
-
-
-
-
-
-
-
Lecture#28(
pdf): Phase noise in ring oscillators (contd.), Circuit design of PLL building blocks (PFD)
-
Lecture#30(
pdf): Circuit design of PLL building blocks (Charge Pump)
Lecture#31(
pdf): Circuit design of PLL building blocks (Charge Pump) contd.
Assignments
Assignments will be posted below. You are expected to solve them on your own. You should submit each one by 09:00AM of the due date mentioned. Copying will carry strict penalties.
Course contents
Topics include analog and digital integer-N phase-locked loops (PLLs). Building blocks include phase/frequency detectors, charge-pump, LC/ring-oscillators, multi-modulus frequency dividers, active/passive loop-filter, etc.
Objectives
To develop intuition behind frequency synthesizer design, learning mathematical basis behind operation, and realizing PLLs at architecture and transistor level.
References
F. Gardner, Phaselock Techniques, John Wiley & Sons, 2005.
W. Egan, Phase-Lock Basics, John Wiley & Sons, 2008.
R. Best, Phase-Locked Loops : Design, Simulation, and Applications, McGraw Hill, 2003.
Pre-requisites
Attendance
Attendance will be strictly enforced.