Integrated Circuits and Systems group, IIT Madras

Integrated Circuits and Systems group, IIT Madras

Welcome to the homepage of the Integrated Circuits and Systems group in the Department of Electrical Engineering at IIT Madras. We are located in a beautiful wooded campus in southern Chennai.

Our faculty and students are involved in research in the areas of analog, mixed signal, and RF design, analysis and simulation of noise in circuits, VLSI DSP architectures, and reconfigurable computing. Click on the tabs above to find out more about us and our research.

We regularly have openings for students in our research group. If you wish to study here, go through this page for more information and contact the faculty member working in your area of interest. Here is a short video about our group:

MS/PhD at IIT Madras and GATE 2018

A number of MS/PhD positions are available in our group. Bachelors students applying for MS or (direct) PhD require a GATE score. Students who intend to apply to these positions, including those in the final year of their bachelors program, are urged to register for GATE 2018 in EC/EE/IN. For these research positions, selections are through a test and interview and GATE score is used only for shortlisting for the test and interview. GATE requirement is waived for MS and direct PhD applicants from IITs with CGPA ≥ 8.0. GATE requirement is waived for direct PhD applicants from CFTIs with CGPA ≥ 8.0. See this link and this link for detailed shortlisting criteria used this year.


  • Asish, Ashutosh, Chintan, Gautham, Iraban, Kishore, Raghavendra, and Venkata Sesha Rao have joined the ICS group. A warm welcome to all of them.
  • Online courses Basic Electrical Circuits and Analog circuits will be run on NPTEL starting 24th July 2017. Click on the respective links to register. Registration deadline is 24th July.
  • Our recorded lectures will now become available on our YouTube channel. They will continue to be available at
  • Anoop Narayan Bhat received the 2016 Technoinventor award in the masters category from the India Electronics and Semiconductor Association at their 2017 vision summit.
  • The paper Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM by Sumit Kumar and Nagendra Krishnapura will be presented at the 2017 International Symposium on circuits and Systems to be held in Baltimore, USA in May 2017.
  • The paper On Linear Periodically Time Varying (LPTV) Systems with Modulated Inputs, and Their Application to Smoothing Filters by Shanthi Pavan will be presented at the 2017 International Symposium on circuits and Systems to be held in Baltimore, USA in May 2017.

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  • The paper A 500Mb/s, 200pJ/bit die-to-die bidirectional link with 24kV surge isolation and 50kV/s CMR using resonant inductive coupling in 180nm CMOS by Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura will be presented at the 2017 International Solid-State Circuits Conference to be held in San Francisco, USA in Feb. 2017.
  • The paper A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset by Ashwin Kumar R. S., Debasish Behera, and Nagendra Krishnapura was presented at the 2017 VLSI Design Conference held in Hyderabad in Jan. 2017.