- Harikumar Ganesan, Boby George, Sankaran Aniruddhan and Saleem Haneefa, “A Dual Slope LVDT-to-Digital Converter”,
*IEEE Sensors Journal*, 2018, early access. - Anantha MS, Abhishek Kumar and Sankaran Aniruddhan, “A Compact +10/+5dBm 800/2600MHz LTE Driver Amplifier with Ground-Bounce Reduction”,
*IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)*, 2018, early access. - Arpan Thakkar, Srinivas Theertham and Sankaran Aniruddhan, “Phase Noise Analysis of Bipolar Class-C VCOs with Delay in Oscillator Loop”,
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, 2018, early access. - Ahmad Sharkia, Sankaran Aniruddhan, Shahriar Mirabbasi and Sudip Shekhar, “A Compact, Voltage-Mode Type-I PLL with Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter”,
*IEEE Transactions on Circuits and Systems I*, 2018, early access. - G. Vinodhini, Boby George, Sankaran Aniruddhan, J. Dhurga Devi and P.V. Ramakrishna, “Performance Analysis of Oscillator Based Read-out Circuit for LVDT”,
*IEEE Transactions on Instrumentation & Measurement*, 2018, early access. - R. S. Ashwin Kumar, Debasish Behera, and Nagendra Krishnapura, “Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion,”
*IEEE Transactions on Circuits and Systems I: Regular Papers*, 2018. DOI: 10.1109/TCSI.2018.2854707. - Abhishek Bhat and Nagendra Krishnapura, “On-Chip Static Phase Difference Measurement Circuit with Gain and Offset Calibration,”
*IEEE Transactions on Circuits and Systems II: Express Briefs*, 2018. DOI: 10.1109/TCSII.2018.2842101. - S.Manivannan and S.Pavan,“Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, October 2018. - S.Pavan and E.Klumperink, “Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, October 2018. - S. Javvaji, V.Singhal, V.Menezes and S.Pavan,“Multi-step bias flip rectification for piezo-electric energy harvesting,”
*Proceedings of the European Solid State Circuits Conference, Dresden, Germany*, Sept. 2018. - A. Kumar and S. Aniruddhan,“A 2.5GHz CMOS Full-Duplex Front-End for Asymmetric Data Networks,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, October 2018. - S.Pavan, “Improved Chopping in Continuous-time Delta-Sigma Converters using FIR Feedback and N-Path Techniques,”
*IEEE Transactions on Circuits and Systems: Express Briefs*, May 2018 (ISCAS 2018 Special Issue). - S.Pavan and S.Baskaran, “What Architecture Should I use for my Continuous-time Delta-Sigma Converter?,”
*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,*Florence. - Peeyoosh Mirajkar, Jagdish Chand, Sankaran Aniruddhan, Srinivas Theertham, “Low Phase Noise Ku-Band VCO with Reduced Frequency Drift Across Temperature,”
*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,*Florence. - Arpan Sureshbhai Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan, “A 27.2GHz Bipolar LC-VCO Using Class-C Biasing to Maximize Achievable Fosc in 130nm BiCMOS,”
*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,*Florence. - Abhishek Kumar, Radha Krishna Ganti, Sankaran Aniruddhan, “A Same-Channel Full-Duplex Receiver Using Direct RF Sampling,”
*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,*Florence. - S.Pavan,“FIR Feedback in Continuous-time Delta Sigma Converters,”
*Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,*San Diego. - S.Manivannan and S.Pavan,“A 1 MHz Bandwidth, Filtering Continuous-Time Delta-Sigma ADC with 36 dBFS Out-of-Band IIP3 and 76 dB SNDR,”
*Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,*San Diego. - S.Pavan,“Practical Design and Simulation Techniques for Continuous-time Delta Sigma Converters,”
*Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,*San Diego. - I. Mondal and N. Krishnapura, “Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters,”
*IEEE Transactions on Circuits and Systems I: Regular Papers*, To appear. DOI: 10.1109/TCSI.2018.2799080 - Abhishek Bhat and Nagendra Krishnapura, “Low 1/f
^{3}Phase Noise Quadrature LC VCOs”,*IEEE Transactions on Circuits and Systems: Regular Papers*, To appear. DOI: 10.1109/TCSI.2017.2782247 - S.Pavan and E.Klumperink, “Analysis of the Effect of Source Capacitance and Inductance on N-path Mixers and Filters,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, May 2018. - P. Mirajkar, J. Chand, S. Aniruddhan and S. Theertham,“Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design,”
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 26, no.3, March 2018. - A.Jain and S. Pavan, “Continuous-time delta-sigma modulators with time-interleaved FIR feedback,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, Feb. 2018. - Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer “80Kb Logic Embedded High-K Charge Trap Transistor based Multi-Time-Programmable Memory with no Added Process Complexity” IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 949-960, March 2018.

- Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Hairong Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil and Shanthi Pavan, “A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD,”
*IEEE Journal of Solid State Circuits*, December 2017. - Gaurav Agrawal and Sankaran Aniruddhan, “A Modified Bias Scheme for High-Gain Low-Noise Folded Cascode OTAs”,
*IEEE Electron Devices and Solid-State Circuits Conference (EDSSC 2017), October 2017*Hsinchu, Taiwan. - Ramakrishna Avula and Sankaran Aniruddhan, “Low-Voltage 0.5.3GHz Radio Receiver for Multiband Cellular Applications”,
*IEEE Electron Devices and Solid-State Circuits Conference (EDSSC 2017), October 2017*Hsinchu, Taiwan. - Arpan Thakkar, Apoorva Bhatia, Vikram Sharma, Srinivas Theertham and Sankaran Aniruddhan, “A 4-Port Inductor based Compact Dual-core VCO with Improved Phase Noise Performance”,
*IEEE Electron Devices and Solid-State Circuits Conference (EDSSC 2017), October 2017*Hsinchu, Taiwan. - Arpan Thakkar, Srinivas Theertham, Sankaran Aniruddhan, Peeyoosh Mirajkar and Jagdish Chand Goyal, “A 3.9 - 4.5GHz Class-C VCO with Accurate Current Injection Based on Capacitive Feedback,”
*European Microwave Integrated Circuits Conference (EuMIC), October 2017*Nuremberg, Germany. - Sujith Billa, Amrith Sukumaran and Shanthi Pavan, “Analysis and Design of Continuous-time Delta-Sigma Modulators Incorporating Chopping,”
*IEEE Journal of Solid State Circuits*, September 2017. - Shanthi Pavan and Eric Klumperink,“Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, October 2017. - Neha Sinha, Mansour Rachid, Shanthi Pavan and Sudhakar Pamarti,“Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With>+ 31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components,”
*IEEE Journal of Solid State Circuits*, August 2017. - Shanthi Pavan, “Analysis of chopped integrators and its application to continuous-time delta-sigma modulator design,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, August 2017. - Saravanan K. and S. Aniruddhan, “Area Efficient Low Power Crystal Oscillator with Automatic Amplitude Control,”
*IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), August 2017*Boston, MA, USA. - Arjun Nadh, Joseph Samuel, Ankit Sharma, Sankaran Aniruddhan, and Radha Krishna Ganti, “A Taylor Series Approximation of Self-Interference Channel in Full-Duplex Radios,”
*IEEE Transactions on Wireless Communications*, vol. 16, no.7, July 2017. - Imon Mondal and Nagendra Krishnapura, “A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 μm CMOS.”
*IEEE J. Solid State Circuits*, IEEE Early access(paper) - Sumit Kumar and Nagendra Krishnapura, “Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM”,
*Proc. 2017 IEEE ISCAS*, Baltimore, USA, May 2017. - Shanthi Pavan, “ On Linear Periodically Time Varying (LPTV) Systems with Modulated Inputs, and Their Application to Smoothing Filters”,
*Proc. 2017 IEEE ISCAS*, Baltimore, USA, May 2017. - Vinodhini G., Sankaran Aniruddhan, Boby George, Dhurga Devi J. and Ramakrishna P.V., “A Simple and Efficient Oscillator Based Read-out Scheme for LVDT,”
*IEEE Instrumentation and Measurement Technology Conference (I2MTC), May 2017*Torino, Italy. - Sreenivasa Mallia S, Sreeram NS, Sudhir Adinarayana, and Sankaran Aniruddhan, “A Self-Powered 50Mbps OOK Transmitter for Opto-Isolator LED Emulation,”
*IEEE Journal of Solid-State Circuits*, vol. 52, no. 3, March 2017. - Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura, “ A 500Mb/s, 200pJ/bit die-to-die bidirectional link with 24kV surge isolation and 50kV/s CMR using resonant inductive coupling in 180nm CMOS,”
*2017 International Solid-State Circuits Conference*, San Francisco, USA, Feb. 2017. - R. S. Ashwin Kumar and Nagendra Krishnapura, “A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset,”
*30th International Conference on VLSI Design*, Hyderabad, India, Jan. 2017.

- Abhishek Kumar, Sankaran Aniruddhan, and Radha Krishna Ganti, “An Asymmetric 2.4 GHz Directional Coupler using Electrical Balance,”
*IEEE Microwave and Wireless Component Letters*, vol. 26, no. 12, December 2016. - Gaurav Agrawal, Sankaran Aniruddhan, and Radha Krishna Ganti, “A Compact Mixer-First Receiver with >24dB Self-Interference Cancellation for Full-Duplex Radios,”
*IEEE Microwave and Wireless Component Letters*, vol. 26, no. 12, December 2016. - Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar Khan, Toshiaki Kirihata, Subramanian S. Iyer: A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. J. Solid-State Circuits 51(1): 230-239 (2016)
- Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer: 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2
- Rakshitdatta K. S., Yujendra Mitikiri, and Nagendra Krishnapura, “A 12.5 mW, 11.1 nV/rtHz, −115dB THD, < 1 µs Settling, 18 bit SAR ADC Driver in 0.6µm CMOS,”
*IEEE Transactions on Circuits and Systems II-Express Briefs*, vol. 63, no. 5, pp. 443-447, May 2016. - Abhishek Bhat and Nagendra Krishnapura, “A Tail-Resonance Calibration Technique for Wide Tuning Range LC VCOs”,
*Proc. 2016 ISCAS*, Montreal, May 2016. - Shanthi Pavan, “Continuous-Time Delta Sigma Modulators with Dual Switched Capacitor Resistor DACs”,
*Proc. 2016 ISCAS*, Montreal, May 2016. - Aparna Girija and Aniruddhan S., “A Compact Dual-Band 5dBm RF Power Amplifier for Cellular Applications”,
*Proc. 2016 ISCAS*, Montreal, May 2016. - A. Sukumaran and S. Pavan, “Design of Continuous-time Delta Sigma Modulators with Dual Switch Capacitor Return-to-Zero DACs”
*IEEE Journal of Solid State Circuits*, July 2016. - A. Jain and S. Pavan, “ A 13.3mW 60MHz Bandwidth, 76dB DR 6GS/s CTDSM with Time Interleaved FIR Feedback”
*Symposium on VLSI Circuits , Honolulu, Hawaii*, June 2016 (to appear). - S. Pavan and R. Rajan, “ Design Considerations for Filtering Delta Sigma Converters ”,
*Proceedings of the Workshop on Advanced Analog Circuit Design*, 24th-27th April 2016, Villach, Austria. - S. Billa, A. Sukumaran and S. Pavan, “A 280uW, 24kHz BW, 98.5 dB SNDR, chopped single-bit CTDSM achieving < 10\,Hz 1/f noise corner without chopping artifacts ”
*International Solid State Circuits Conference*, 1st-4th February 2016, San Francisco, USA. - K. Singh and S. Pavan, “ A 14 bit Dual Channel Incremental Continuous-time Delta Sigma Modulator for Multiplexed Data Acquisition”
*29th International Conference on VLSI Design*, 4-8 January 2016, Kolkata, India. - S. Pavan and N. Krishnapura, “Demystifying Time-Varying Systems,”
*Half Day Tutorial at the 29th International Conference on VLSI Design*, 4-8 January 2016, Kolkata, India. - R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu,“A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,”
*IEEE Trans. Circuits Syst. I*(accepted). - A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,”
*IEEE J. Solid-State Circuits*, vol. 51, no. 8, pp. 1771-1784, Aug. 2016. - G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5-Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,”
*IEEE J. Solid-State Circuits*, vol. 51, no. 2, pp. 428-439, Feb. 2016. - G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar, R. Nandwana, and P. K. Hanumolu,“A 16Mb/s-8Gb/s, 14.1-7.2pJ/bit source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS,”
*ISSCC Digest of Technical Papers*, pp. 398-399, Feb. 2016.

- J. d. l. Rosa, K. Pun, R. Schreier, and S. Pavan. Next-generation delta-sigma converters : Trends and perspectives. IEEE Journal of Emerging Topics in Circuits and Systems (JETCAS), 5(4):Dec, 2015.
- Amrith Sukumaran and Shanthi Pavan, “A Continuous-Time Delta Sigma Modulator with 91 dB Dynamic Range in a 2MHz Signal Bandwidth Using a Dual Switched-Capacitor Return-to-Zero DAC,”
*2015 ESSCIRC*, Graz, Austria, Sep. 2015. - Imon Mondal and Nagendra Krishnapura, “Gain enhanced high frequency OTA with on-chip tuned negative conductance load,”
*2015 IEEE ISCAS*, pp. 2085 - 2088, Lisbon, Portugal, May. 2015. - Sandeep Krishnan and Shanthi Pavan, “A 10 Gbps eye opening monitor in 65nm CMOS,”
*2015 IEEE ISCAS*, pp. 3028 - 3031, Lisbon, Portugal, May. 2015. - Naga Rajesh and Shanthi Pavan, “Programmable analog pulse shaping for ultra-wideband applications,”
*2015 IEEE ISCAS*, pp. 461 - 464, Lisbon, Portugal, May. 2015. - Rakshitdatta K. S. and Nagendra Krishnapura, “On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback,”
*28th International Conference on VLSI Design*, pp. 244-248, Bangalore, India, Jan. 2015. - Imon Mondal and Nagendra Krishnapura, “Accurate Constant Transconductance Generation Without Off-chip Components,”
*28th International Conference on VLSI Design*, pp. 249-253, Bangalore, India, Jan. 2015. - T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7Gb/s embedded clock transceiver for energy proportional links,”
*IEEE J. Solid-State Circuits*, vol. 50, no. 12, pp. 3101-3119, Dec. 2015. - R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, “A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method,”
*IEEE J. Solid-State Circuits*, vol. 50, no. 4, pp. 882-895, Apr. 2015. - A. Elkholy, S. Saxena, and P. K. Hanumolu, “A 4mW wide bandwidth ring-based fractional-N DPLL with 1.9psrms integrated-jitter,”
*IEEE Custom Int. Circuits Conf.*, pp. 1-4, Sept. 2015. - S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, “A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,”
*IEEE VLSI Circuits Sym. Tech. Papers*, pp. 1-2, June 2015. - T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7Gb\/s rapid on/off embedded clock serial link transceiver with 20ns power-on time, 740uW off-state power for energy proportional links in 65nm CMOS,”
*ISSCC Digest of Technical Papers*, pp. 64-66, Feb. 2015. - S. J. Kim, R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski, and P. K. Hanumolu, “A 4-phase 30-70 MHz switching frequency buck converter using a time-based compensator,” IEEE J. Solid-State Circuits, vol.50, no.12, pp.2814-2824, Dec. 2015.
- S. J. Kim, Q. Khan, M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre, and P. K. Hanumolu, “High frequency buck converter design using time-based control techniques,” IEEE J. Solid-State Circuits,vol. 50, no. 4, pp. 990-1001, Apr. 2015.
- S. J. Kim; R. K. Nandwana, Q. Khan, R. Pilawa-Podgurski, P. K. Hanumolu, “A 1.8V 30-to-70MHz 87% Peak Efficiency 0.32mm2 4-Phase Time-Based Buck Converter Consuming 3uA/MHz Quiescent Current in 65nm CMOS, ” 2015 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 22-26 Feb. 2015.

- Debasish Behera and Nagendra Krishnapura, “A 2-Channel 1MHz BW, 80.5dB DR ADC Using ΔΣ Modulator and Zero-ISI Filter,”
*Proceedings of the 40th European Solid-State Circuits Conference*, Venice, Italy, Sep. 2014. - R. Rajan and S.Pavan, “Design Techniques for Continuous-Time Delta Sigma ADCs with Embedded Active Filtering,”
*IEEE Journal of Solid State Circuits,*to appear. - A. Sukumaran and S.Pavan, “Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback,”
*IEEE Journal of Solid State Circuits,*Nov. 2014. - S.Pavan and R. Rajan,“ Simplified Analysis and Simulation of the STF, NTF and Noise in CTDSMs,”
*IEEE Transactions on Circuits and Systems:Express Briefs,*September 2014. - S.Pavan and R. Rajan,“ Interreciprocity in linear periodically time varying networks with sampled outputs,”
*IEEE Transactions on Circuits and Systems:Express Briefs,*September 2014. - Nagendra Krishnapura and K. S. Rakshitdatta, “A Model Agnostic Technique for Simulating Per-Element Distortion Contributions,”
*IEEE Transactions on Circuits and Systems I: Regular Papers*, Aug. 2014. - N. Rajesh and S.Pavan,“ Design of Lumped Component Programmable Delay Elements for Ultra-Wideband Beamforming,”
*IEEE Journal of Solid State Circuits,*August 2014. - S. Pavan, “Efficient estimation of Signal and Noise Transfer Functions in a Continuous-time Delta Sigma Modulator,”
*International Symposium on Circuits and Systems (ISCAS),*Melbourne, June 2014. - S. Pavan, “Continuous time Delta Sigma Modulator Design using the Method of Moments,”
*IEEE Transactions on Circuits and Systems : Regular Papers,*June 2014. - A. Jain and S. Pavan, “ Characterization Techniques for High Speed Oversampled Data Converters,”
*IEEE Transactions on Circuits and Systems : Regular Papers,*May 2014. - Radha Rajan and S. Pavan, “A 5mW CT ΔΣ ADC with Embedded 2nd-Order Active Filter and VGA Achieving 82dB DR in 2MHz BW,”
*International Solid State Circuits Conference (ISSCC),*San Francisco, February 2014. - N. Krishnapura, “Pedagogy of Negative Feedback Circuits,”
*Half Day Tutorial at the 27th International Conference on VLSI Design*, 5-9 January 2014, Mumbai, India. - S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,”
*IEEE J. Solid-State Circuits*, vol. 49, no. 8, pp. 1827-1836, Aug. 2014. - G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,”
*IEEE J. Solid-State Circuits*, vol. 49, no. 4, pp. 1036-1047, Apr. 2014. - R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, “A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement,”
*IEEE VLSI Circuits Sym. Tech. Papers*, pp. 1-2, June 2014. - M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi, and P. K. Hanumolu, “A 4.4-5.4GHz digital fractional-N pll using ΔΣ frequency-to-digital converter,”
*IEEE VLSI Circuits Sym. Tech. Papers*, pp. 1-2, June 2014. - A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. K. Hanumolu, “A 20-to-1000MHz 14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS,”
*ISSCC Digest of Technical Papers*, pp. 272-273, Feb. 2014. - G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,”
*ISSCC Digest of Technical Papers*, pp. 150-151, Feb. 2014. - Q. Khan, S. J. Kim; M. Talegaonkar, A. Elshazly, A. Rao, N. Griesert, G. Winter, W. McIntyre and P. K. Hanumolu, “A 10-25MHz, 600mA buck converter using time-based PID compensator with 2uA/MHz quiescent current, 94% peak efficiency, and 1MHz BW,” VSLI Symp., June 2014, Honolulu.

- Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction for Skewed Gaussian Variations. International Workshop on Physics of Semiconductor Devices 207-209 (December 2013)
- S. Pavan, “Systematic Derivation of Well Known Analog Circuits,”
*Tutorial at IEEE PRIME-Asia*, Vishakapatnam, Dec. 2013. - M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, “Compact silicon biosensor for the clinical range estimation of blood serum triglyceride, ”
*Proceedings of the IEEE Sensors Conference,*Baltimore, Nov. 2013. - A. Sukumaran and S. Pavan, “A 280 μW Audio Continuous-Time Modulator with 103 dB DR and 102 dB A-Weighted SNR,”
*Proceedings of the 2013 Asian Solid State Circuits Conference*, Singapore, Nov. 2013. - A. Sukumaran, K. Karanjkar, S. Jhanwar, N. Krishnapura and S. Pavan, “A 1.2 V 285 μA Analog Front End Chip for a Digital Hearing Aid in 0.13μm CMOS,”
*Proceedings of the 2013 Asian Solid State Circuits Conference*, Singapore, Nov. 2013. - N. Krishnapura and Rakshitdatta K. S., “A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions,”
*Proceedings of the 2013 IEEE Custom Integrated Circuits Conference*, September 2013. - N. Rajesh and S. Pavan, “A Lumped Component Programmable Delay Element for Ultra-Wideband Beamforming,”
*Proceedings of the 2013 IEEE Custom Integrated Circuits Conference*, September 2013. - T.Nandi, K.Boominathan and S.Pavan, “Continuous-time Delta Sigma Modulators with Enhanced Linearity and Reduced Clock Jitter Sensitivity using the Switched Capacitor Return to Zero DAC”,
*IEEE Journal of Solid State Circuits*, August 2013 (to appear). - M.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan, “A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit”,
*IEEE Sensors Journal*, May 2013. - A. Jain and S. Pavan, “Improved Characterization of High Speed Continuous-Time Delta Sigma Modulators Using a Duobinary Test Interface,”
*Proceedings of the International Symposium on Circuits and Systems (ISCAS)*, Beijing, May 2013**(winner of the Best Student Paper Award at ISCAS 2013)**. - S. Pavan, “A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator,”
*IEEE Transactions on Circuits and Systems : Express Briefs*, February 2013. - S. Pavan, “Simulation Techniques in Data Converter Design,”
*Tutorial at the International Solid State Circuits Conference (ISSCC)*, February 2013. - S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s 3.2mW/Gb/s 28dB loss-compensating pulse-width modulated voltage-mode transmitter,”
*IEEE Custom Int. Circuits Conf.*, pp. 1-4, Sept. 2013. - R. K. Nandwana, S. Saxena, and P. K. Hanumolu, “A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC,”
*IEEE VLSI Circuits Sym. Tech. Papers*, pp. 156-157, June 2013. - G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu,“A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR,”
*IEEE VLSI Circuits Sym. Tech. Papers*, pp. 278-279, June 2013.

- Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1920-1924 (2012)
- P. Shettigar and S.Pavan, “Design Techniques for Wideband Continuous-time Delta-Sigma Modulators with FIR Feedback DACs,”
*IEEE Journal of Solid State Circuits*, December 2012. - T. Nandi, K. Boominathan and S.Pavan, “ A Continuous-time Delta Sigma Modulator with 87dB Dynamic Range in a 2MHz Signal Bandwidth Using a Switched-Capacitor Return-to-Zero DAC,”
*Proceedings of the 2012 Custom Integrated Circuits Conference (CICC)*, San Jose, California, 2012. - R.S.Rajan and S.Pavan, “Device Noise in continuous-time delta-sigma modulators,”
*IEEE Transactions on Circuits and Systems: Regular Papers*, September 2012. - V. Singh, N. Krishnapura, S.Pavan, B.Vigraham, D.Behera and N.Nigania “A 16 MHz BW 75 dB DR CT Delta Sigma ADC Compensated for More Than One Cycle Excess Loop Delay,”
*IEEE Journal of Solid State Circuits*,August 2012. - A.Jain, N. Muthusubramaniam and S.Pavan, “Analysis and Design of a High Speed Continuous Time Delta Sigma Modulator Using the Assisted Opamp Technique,”
*IEEE Journal of Solid State Circuits*, July 2012. - R.S.Rajan and S.Pavan, “Noise in CT DS Modulators with Switched Capacitor Feedback DACs,”
*Proceedings of the 2012 IEEE International Symposium on Circuits and Systems (ISCAS)*, Seoul, Korea, 2012. - P. Shettigar and S.Pavan, “A 15mW 3.6GS/s CT-Delta Sigma ADC with 36MHz Bandwidth and 83dB Dynamic Range in 90nm CMOS,”
*Proceedings of the 2012 IEEE International Solid State Circuits Conference (ISSCC)*, San Francisco, February 2012.**(Winner of the ISSCC 2012 Silk Road Award)** - R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, “A 75-dB SNDR, 5-MHz bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 16mW power,”
*IEEE Trans. Circuits Syst. I*, vol. 59, no. 8, pp. 1614-1625, Aug. 2012. - S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 12.5-bit 4MHz 13.8mW MASH ΔΣ modulator with multirated VCO-based ADC,”
*IEEE Trans. Circuits Syst. I*, vol. 59, no. 8, pp. 1604-1613, Aug. 2012. - Q. Khan, A. Elshazly, S. Rao,R. Inti and P. K. Hanumolu, “A 900mA 93% Efficient 50uA Quiescent Current Fixed Frequency Hysteretic Buck Converter Using a Highly Digital Hybrid Voltage- and Current-mode Control,” VSLI Symp., June 2012, Honolulu.

- Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach, International Workshop on Physics of Semiconductor Devices, 2011 [
**Poster**] - Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera, “A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay,”
*Proceedings of the 2011 IEEE Custom Integrated Circuits Conference*, San Jose, September 2011. - A. Jain, M. Venkatesan and S. Pavan, “A 4mW 1GS/S Continuous-Time DeltaSigma Modulator with 15.6MHz Bandwidth and 67dB Dynamic Range”
*Proceedings of the European Solid State Circuits Conference*, Helsinki, September 2011. - S. Thyagarajan, S. Pavan and P. Sankar, “Active Filters using the Gm-Assisted OTA-RC Technique”,
*IEEE Journal of Solid State Circuits,*July 2011. (paper) - Chembiyan Thambidurai and Nagendra Krishnapura, “On Pulse Position Modulation and its Application to PLLs for Spur Reduction”,
*IEEE Transactions on Circuits and Systems I-Regular Papers*, vol. 58, no. 7, pp. 1483-1496, July 2011. - S. Aniruddhan, Sudip Shekhar and David J. Allstot, “A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing”,
*IEEE Transactions on Circuits and Systems I-Regular Papers*, vol. 58, no. 5, pp. 860-867, May 2011.(paper) - S. Pavan, “On Continuous-time Delta-Sigma Modulators with Return-to-Open DACs”,
*IEEE Transactions on Circuits and Systems : Express Briefs, May 2011.(paper)* - Nagendra Krishnapura, Abhishek Agrawal, and Sameer Singh, “A High IIP3 Third Order Elliptic Filter with Current Efficient Feedforward Compensated Opamps,”
*IEEE Transactions on Circuits and Systems II-Express Briefs*, vol. 58, no. 4, pp. 205-209, April 2011. (paper) - Nagendra Krishnapura, “Electronic Time Stretching for Fast Digitization,”
*2011 International Symposium on Circuits and Systems (ISCAS)*, Rio de Janeiro, Brazil, 15-18 May 2011. - S. Pavan, “The Inconvenient Truth about Alias Rejection in Continuous-time Delta-Sigma Modulators”,
*Proceedings of the IEEE International Symposium on Circuits and Systems,*May 2011. - A. Cicalini, S. Aniruddhan, R. Apte, F. Bossu, O. Choksi, D. Filipovic, K. Godbole, T.P. Hung, C. Komninakis, D. Maldonado, C. Narathong, B. Nejati, D. O'Shea, X. Quan; R. Rangarajan, J. Sankaranarayanan, A. See, R. Sridhara, B. Sun; W. Su; K. van Zalinge, G. Zhang; K. Sahota, “A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor”,
*Proceedings of the 2011 IEEE International Solid-State Circuits Conference*, San Francisco, February 2011. (paper) - S. Pavan, “Alias Rejection of Continuous-time Delta-Sigma Converters with Switched-Capacitor Feedback DACs”,
*IEEE Transactions on Circuits and Systems : Regular Papers,*February 2011. (paper) - R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, “A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW,”
*IEEE Custom Int. Circuits Conf.*, pp. 1-4, Sept. 2011. - S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer,”
*IEEE Custom Int. Circuits Conf.*, pp. 1-4, Sept. 2011. - S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, P.K. Hanumolu, “A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique,” IEEE Journal of Solid-State Circuits, Volume: 46, Issue: 12, pp 2772- 2783, Dec. 2011.
- Q. Khan, S. Rao, D. Swank, A. Rao, W. McIntyre, S. Bang, P.K. Hanumolu, “A 3.3V 500mA Digital Buck-Boost Converter with 92% Peak Efficiency Using Constant ON/OFF Time Delta-Sigma Fractional-N Control,” 37th European Solid-State Circuits Conference (ESSCIRC), 12-16 Sept. 2011, Helsinki, Finland.
- S. Rao. Q. Khan, S. Bang, D. Swank, A. Rao, W. McIntyre, P.K. Hanumolu, “A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing,” 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, 20-24 Feb. 2011.

- Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1056-1069 (2010)
- S. Pavan, “High-Performance Continuous-time Delta Sigma Converters,” Educational Sessions of the Custom Integrated Circuits Conference, San Jose, USA, 2010.
- S. Pavan, ``Design Techniques for High-Performance Continuous-time Delta Sigma Conversion,“ half day tutorial at the European Solid State Circuits Conference, Seville, Spain, 2010.
- S. Thyagarajan, S. Pavan and P. Sankar, ``Low Distortion Active Filter Design using the Gm-Assisted OTA-RC Technique,”
*at the European Solid State Circuits Conference, Seville, Spain*, September 2010.(paper) - V. Singh, N. Krishnapura, S. Pavan, “Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time ΔΣ Modulators,”
*IEEE Transactions on Circuits and Systems II: Express Briefs*, vol. 57, no. 9, pp. 676-680, Sep. 2010. (paper) - S. Pavan, “Efficient simulation of weak nonlinearities in continuous-time oversampling converters”,
*IEEE Transactions on Circuits and Systems : Regular Papers,*August 2010. (paper) - S. Pavan and P. Sankar, “Power reduction in continuous-time Delta-Sigma Modulators using the assisted opamp technique”,
*IEEE Journal of Solid State Circuits,*July 2010. (paper)**(most read paper in the IEEE Journal of Solid State Circuits in July 2010, and 11th most downloaded paper from ALL of IEEEXplore in July 2010)**link - S. Pavan, “Understanding weak nonlinearities in continuous-time oversampling converters”,
*IEEE International Symposium on Circuits and Systems (ISCAS),*Paris, May 2010. - K. Reddy and S.Pavan, “A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range”,
*Analog Integrated Circuits and Signal Processing,*June 2010. (paper) - S. Pavan, “Systematic design centering of continuous-time oversampling converters”,
*IEEE Transactions on Circuits and Systems : Express Briefs,*March 2010 (paper) - S. Bang, D. Swank, A. Rao, W. McIntyre, Q. Khan, P.K. Hanumolu, “A 1.2A 2MHz Tri-Mode Buck-Boost LED Driver With Feed-Forward Duty Cycle Correction,” IEEE Custom Integrated Circuit Conference (CICC-2010), San Jose, California. September 2010.
- K. Jayaraman, Q. Khan, B. Chi, W. Beattie, Z. Wang, P. Chiang, “A Self-Healing 2.4GHz LNA with On-Chip S11S21 MeasurementCalibration for In-Situ PVT Compensation,” Radio Frequency Integrated Circuits (RFIC) Symposium, Anaheim, CA, May 2010.

- S.Pavan and P.Sankar, “A 110-microwatt Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB Dynamic Range”,
*European Solid State Circuits Conference (ESSCIRC),*Athens, Greece, September 2009 (paper). - Y.Darhwekar, R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, “A Digitally Assisted Baseband Filter with 9 MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain”,
*International Symposium on Circuits and Systems (ISCAS),*Taipei, Taiwan, 24-27 May 2009.(paper) - S.Saxena,P.Sankar and S.Pavan, “Automatic Tuning of Time Constants in Single-bit Continuous-time Delta Sigma Modulators”,
*International Symposium on Circuits and Systems (ISCAS),*Taipei, Taiwan, 24-27 May 2009. (paper) - V. Vasudevan, “Analysis of Clock Jitter in Continuous-Time Sigma–Delta Modulators,”,
*IEEE Transactions on Circuits and Systems I : Regular Papers*, March 2009. (paper) - T.Laxminidhi,V.Prasadu and S.Pavan, “Widely Programmable High Frequency Active-RC Filters in CMOS Technology”,
*IEEE Transactions on Circuits and Systems I : Regular Papers,*(paper) February 2009. - N.Krishnapura and S.Pavan, “Negative Feedback System and Circuit Design”, Full Day Tutorial at the International Conference on VLSI Design, 5-9 January 2009, New Delhi, India. (Lecture and notes)

- Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electronics 4(3): 301-319 (2008)
- Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur: Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. VLSI Design 2008: 667-672
- Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind: Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. VLSI Design 2008: 685-691
- V.Hareesh, S.Pavan and E.Bhattacharya, “Readout Circuit Design for an EISCAP Biosensor”,
*IEEE Biomedical Circuits and Systems Conference,*November 2008.(paper) - S.Pavan, “Excess Loop Delay Compensation in Continuous-time Delta Sigma Modulators”,
*IEEE Transactions on Circuits and Systems II : Express Briefs, November 2008.(paper).* - K. Reddy and S.Pavan, “A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range”,
*Proceedings of the European Solid State Circuits Conference, Edinburgh*, September 2008.(paper) - S. Pavan, “Power and Area Efficient Adaptive Equalization at Microwave Frequencies”,
*IEEE Transactions on Circuits and Systems I : Regular Papers,*July 2008.(paper) - Sudip Shekhar, Jeffrey S. Walling, S. Aniruddhan, and David J. Allstot, “CMOS VCO and LNA using Tuned-Input Tuned-Output circuits”,
*IEEE Journal of Solid-State Circuits*, vol. 43, no. 5, pp. 1177-1186, May 2008.(paper) - S. Pavan, “Power and Area Efficient Analog Adaptive Equalization”,
*IEEE International Symposium on Circuits and Systems (ISCAS)*, Seattle, May 2008.(paper) - K. Balemarthy and S. Pavan, “Signal Processing for Optical Fiber Communication”, Tutorial at the National Conference on Communication, February 1-3, Bombay, India.slides
- S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, “A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications,”
*IEEE Journal of Solid State Circuits*, February 2008.(paper) - S. Pavan and N. Krishnapura, “Oversampling Analog-to-Digital Converters”, Full Day Tutorial at the International Conference on VLSI Design, 4-8 January 2008, Hyderabad, India. (Lecture and notes)
- A. Kokrady, C. P. Ravikumar and N. Chandrachoodan, “Memory Yield Improvement through Multiple Test Sequences and Application aware Fault Models”,
*21st International Conference on VLSI Design, VLSI 2008, Hyderabad, India*, January 2008.

- P. Sankar and S. Pavan, “Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators”,
*IEEE Transactions on Circuits and Systems : Express Briefs*, December 2007.(paper) - D.J. Allstot, S. Aniruddhan, M. Chu, N.M. Neihart, D. Ozis, S. Shekhar, and J.S. Walling, “Low Phase Noise CMOS Voltage-controlled Oscillators”, (Invited Paper)
*Proceedings of 7th International Conference on ASIC (ASICON 2007)*, Guilin, China, October 2007.(paper) - K. Reddy and S. Pavan, “Fundamental Limitations of Continuous-time Delta Sigma Modulators due to Clock Jitter”,
*IEEE Transactions on Circuits and Systems : Regular Papers*, October 2007.(paper) - G. Kannan, N. Chandrachoodan and S. Srinivasan, “Rapid Abstract Control Model for Signal Processing Implementation”,
*IEEE Workshop on Signal Processing Systems, SIPS 2007, Shanghai, China*, October 2007, pp. 418-423. - T. Laxminidhi, V. Prasadu and S. Pavan, “A Low Power 44-300 MHz Programmable Active-RC Filter in 0.18um CMOS”,
*Proceedings of the Custom Integrated Circuits Conference*, San Jose, September 2007.(paper) - S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, “A 90 microwatt 15-bit Continuous-time Sigma Delta ADC for Digital Audio”,
*Proceedings of the European Solid State Circuits Conference*, Munich, September 2007.(paper) - S. Pavan and T. Laxminidhi, “Accurate Characterization of Integrated Continuous Time Filters”,
*IEEE Journal of Solid State Circuits, August 2007.(paper)* - K. N. Parashar and N. Chandrachoodan, “A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation”,
*17th International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam*, August 2007, pp. 792-795. DOI: 10.1109/FPL.2007.4380770. - T. Laxminidhi and S. Pavan, “Efficient Design Centering of High Frequency Continuous Time Filters”,
*IEEE Transactions on Circuits and Systems : Regular Papers, July 2007.(paper)* - S. Shekhar, S. Aniruddhan, and D.J. Allstot, “A Tuned-Input Tuned-Output VCO in 0.18μm CMOS”,
*2007 IEEE RFIC Symposium*, Digest of Papers, pp. 607-610, Honolulu, HI, USA, June 2007.(paper) - T. Laxminidhi and S. Pavan, “Efficiently Design Centering High Frequency Integrated Continuous-time Filters”,
*IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans(paper)* - S. Pavan, “Singly Terminated Transmission Line Filters for High Speed Adaptive Equalization”,
*IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans.(paper)* - S. Pavan and N. Krishnapura, “Automatic Tuning of Time-Constants in Continuous-Time Delta-Sigma Modulators”,
*IEEE Transactions on Circuits and Systems : Express Briefs, April 2007.(paper)* - S. Pavan and R. Tiruvuru, “Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers”
*IEEE Transactions on Circuits and Systems : Regular Papers, February 2007. (paper)*

- K.N.Vikram and V.Vasudevan, “Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures”,
*IEEE Trans. VLSI design*. September 2006.(paper) - V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, “ A Distortion Compensating Flash Analog to Digital Conversion Technique,”
*IEEE Journal of Solid State Circuits*. September 2006. (paper) - S. Pavan and T.Laxminidhi, “ A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters,” Proceedings of the
*IEEE Custom Integrated Circuits Conference*, CICC 2006, San Jose, September 2006.(paper) - S. Pavan and T.Laxminidhi, “ A 70-500 MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects,” Proceedings of the
*IEEE European Solid State Circuits Conference*, ESSCIRC 2006, Switzerland, September 2006. (paper) - S. Murali and S. Pavan,“ Rapid Simulation of Current Steering DACs using Verilog-A,” Proceedings of the
*IEEE Custom Integrated Circuits Conference*, CICC 2006, San Jose, September 2006.(paper) - Ponnmozhi S. and Nitin Chandrachoodan, “Design of Hardware Coprocessor for OTDR Application”, 11th IEEE VLSI Design and Test Symposium, VDAT 2006, Goa, India, August 2006.
- S. Shekhar, S. Aniruddhan and D.J. Allstot, “A Fully-Differential CMOS Clapp VCO for IEEE 802.11a Applications”,
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) - S. Aniruddhan, S. Shekhar and D.J. Allstot, “A Delay Generation Technique for Fast-locking Frequency Synthesizers”,
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) - A. Sharma and S. Pavan,“A Single Inductor Multiple Output Converter with Adaptive Delta Current Mode Control,”
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) - K. Reddy and S. Pavan,“Fundamental Limitations of Continuous-time Delta-Sigma Modulators due to Clock Jitter ,”
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides) - T. Rajesh and S. Pavan, “Transmission Line based FIR Structures for High Speed Adaptive Equalization,”
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides) - K.N. Vikram and V. Vasudevan, Scheduling divisible loads on partially reconfigurable hardware,
*Proc. IEEE Symposium on Field-Programmable Custom Computing Machines*, Poster Summary, April 2006. - P. Rajesh Kumar, K. Sridharan and S. Srinivasan, A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment, Parallel Computing Journal, Elsevier, Vol. 32, No. 3, March 2006, pp. 205-221.
- Kavish Seth, Viswajith, S. Srinivasan and V. Kamakoti, “Ultra Folded High-Speed Architectures for Reed-Solomon Decoders”, International Conference on VLSI Design, Hyderabad, Jan 2006.
- S. Pavan and S. Shivappa,“ Nonidealities in Traveling Wave and Transversal FIR Filters Operating at Microwave Frequencies ”,
*IEEE Transactions on Circuits and Systems : Regular Papers*, January 2006. (paper) - S. Pavan, P. Easwaran and C. Srinivasan,“System Level Aspects of Analog-to-Digital Converter Designs,”
*International Conference on VLSI Design*, Hyderabad, India, January 2006. (slides) - Q. Khan, G. K. Siddhartha, “A Sequence Independent Power-on-Reset Circuit for Multi-Voltage Integrated Systems, 2006 IEEE International Symposium on Circuits and Systems (ISCAS-2006),” Mar, 2006, Greece.
- Q. Khan, G. K. Siddhartha, D. Tripathi, S. K. Wadhwa, K. Misri, “Techniques for on-chip Process, Voltage and Temperature Detection and Compensation,” 19th International Conference on VLSI Design, Jan. 2006, India.
- Q. Khan, S. K. Wadhwa, K. Misri, “A single Supply Level Shifter for Multi-Voltage Systems,” 19th International Conference on VLSI Design Jan. 2006, India.

- K.N.Vikram and V.Vasudevan, “Hardware-software co-simulation of bus-based reconfigurable systems”,
*Microprocessors and Microsystems*, vol. 29(4), pp 133-144, May 2005. - K.P.Sunil Rafeeque and V.Vasudevan, “ A New Technique for on-chip error estimation and reconfiguration of current steering digital to analog converters”,
*IEEE Trans. Circuits and Systems-I:Regular papers*, Nov. 2005 - S. Pavan and S. Shivappa,“ Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers”,
*IEEE International Symposium on Circuits and Systems*, ISCAS 2005, Kobe , May 2005.(paper) (slides) - S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau,“ Design considerations for Integrated Modulator Drivers in SiGe Technology”,
*International Journal of High Speed Electronics and Systems*, September 2005. - D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar and K. Soumyanath, “Circuit Techniques for CMOS Multiple-Antenna Transceivers”,
*2005 IEEE RFIC Symposium*, Digest of Papers, Long Beach, CA, USA, June 2005.(paper) - D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar,“Recent advances and design trends in CMOS radio frequency integrated Circuits”,
*International Journal of High Speed Electronics and Systems*, vol.15, no.2, pp 377-428, June 2005. - V.Vasudevan, “Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits”,
*Proc. $42^{nd}$ Design Automation Conference*, pp 397-442, June 2005. - S. Aniruddhan and D.J. Allstot, “Architectural Issues in Base-Station Frequency Synthesizers”,
*IEEE International Symposium on Circuits and Systems*, ISCAS 2005, Kobe , May 2005. (paper) - S. Ramachandran and S. Srinivasan, “Design and FPGA Implementation of an MPEG based Video Scalar with reduced on-chip memory utilization”, Journal of Systems Architecture, Elsevier Publications, Vol. 51, pp. 435-450, 2005.
- K.N. Vikram, V. Vasudevan and S.Srinivasan, “Rate-distortion estimation for fast JPEG 2000 compression at low bit-rates”, Electronics Letters, Vol. 41, No. 1, pp. 16-18, Jan 2005.
- S.Singh and S.Srinivasan, “Architecturally efficient FFT pruning algorithm”, Electronics Letters, Vol. 41, No. 23, pp. 1305-1306, Nov. 2005.
- P.Rajesh Kumar, K.Sridharan and S.Srinivasan, “An Efficient Algorithm for Topological Map Construction in a Planar Environment Explored using Proximity Sensors”, Proceedings of the Second IEEE International Conference on Intelligent Sensing and Information Processing (ICISIP 2005), pp. 67-72, Chennai, India, Jan. 2005.

- K.P. Sunil Rafeeque and V.Vasudevan, “A Built-In-Self-Test Scheme for Segmented and Binary Weighted DACs”,
*Journal of Electronic Testing:Theory and Applications*, vol. 20, pp 623-638, Dec. 2004 - K.P.S.Rafeeque and V.Vasudevan, “A Built-in-Self-Test scheme for Digital to Analog Converters”,
*Proc. 17th International Conference on VLSI design*, pp1027-1032, 2004. - K.P.Sunil Rafeeque and V.Vasudevan, “An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC”,
*Proceedings of the 2004 International Symposium on Circuits and Systems*, 2004. ISCAS '04“, vol. 1, pp 281-284, May, 2004 - N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. “The hierarchical timing pair model for multirate DSP applications.”,
*IEEE Transactions on Signal Processing*, 52(5):1209-1217, May 2004. - S. Aniruddhan, M.Chu and D.J. Allstot, “A lateral-BJT-biased CMOS voltage-controlled oscillator”,
*IEEE International Symposium on Circuits and Systems*, ISCAS 2004, Vancouver, May 2004. (paper) - S. Pavan, ” A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits“,
*IEEE International Symposium on Circuits and Systems*, ISCAS 2004, Vancouver , May 2004.(paper) (slides) - S. Pavan, ” Continuous-Time Integrated FIR Filters at Microwave Frequencies“,
*IEEE Transactions on Circuits and Systems-II, Analog and Digital Signal Processing*, January 2004. (paper) - V.Vasudevan “A Time-Domain Technique for Computation of Noise Spectral Density in Linear and Non-Linear Time-Varying Circuits”,
*IEEE Trans. Circuits and Systems-I*, vol 51(2), pp422,433, Feb 2004 - V.Vasudevan “A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory”,
*IEEE Trans. Circuits and Systems-I:Regular papers*, vol.51(11), pp 2174-2178, Nov. 2004 - V.Vasudevan and M.Ramakrishna “Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits”,
*IEEE Trans. Circuits and Systems-I:Regular papers*, vol.51(11), pp 2165-2174, Nov 2004 - Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, Balakuteswar V. Voleti “A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation” International Conference on VLSI Design, Mumbai, Jan 2004.
- Q. Khan, S. K. Wadhwa, K. Misri, “A tunable gm-C filter with low variation across process, voltage and temperature, ” 17th International Conference on VLSI Design, Mumbai, India, Jan, 2004, pp. 539-544.

- N. Krishnapura and Y. Tsividis, “Micropower low-voltage analog filter in a digital CMOS process”,
*IEEE Journal of Solid State Circuits*, vol. 38, no. 6, pp. 1063-1067, Jun. 2003. (paper) - S. Kudszus, A. Shahani, S.Pavan, D. Schaffer and M. Tarsia, ” A 46-GHz Distributed Transimpedance Amplifier using SiGe Bipolar Technology “,
*Proceedings of the International Microwave Symposium*, Philadelphia, May 2003.(paper) - S. Pavan, ” Analog FIR Filters at Microwave Frequencies “,
*Proceedings of the National Conference on Communications*, IIT Madras, Chennai, February 2003.(paper) - V.Vasudevan and M.Ramakrishna, “Computation of Noise Spectral Density in Switched Capacitor Circuits using the Mixed-Frequency-Time Technique”,
*Proc. $40^{th}$ Design Automation Conference*, June 2003 - V.Vasudevan, “A Time-Domain Technique for Computation of Noise Spectral Density in Switched Capacitor Circuits”,
*Proc.of the 2003 International Symposium on Circuits and Systems*, ISCAS 2003, Vol 1., pp 585-588. - Y. Tsividis, N. Krishnapura, Y. Palaskas, L. Toth, “Internally varying analog circuits minimize power dissipation”
*IEEE Circuits and Devices Magazine*, vol. 19, no. 1, pp. 63-72, Jan. 2003. (paper) - Srikar Movva and S. Srinivasan, “A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI implementation”, Sixteenth International Conference on VLSI Design, New Delhi, India, Jan., 2003.
- K. Gupta and S. Srinivasan, ” Reduced Memory Implementation of Modified Serial Watershed Algorithm Based on Queue“, International Conference on information Technology: Coding and Computing, Las Vegas, April 2003.
- A. Kishore and S. Srinivasan, ” A Distributed Memory Architecture for Morphological Image Processing“, International Conference on information Technology: Coding and Computing, Las Vegas, April 2003
- S. Ramachandran and S. Srinivasan, “Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization”, Euromicro symposium on Digital System Design, Belek, Turkey, pp. 206-213, September 2003.
- P.Rajesh Kumar, N. Sudha, S. Srinivasan and K. Sridharan ” A Pipelined Cellular Architecture For Euclidean Distance Transform“, TENCON-2003, Bangalore , 2003
- Q. Khan, D. Dutta, “A Programmable CMOS Bandgap Voltage Reference Circuit using Current Conveyor,” 10th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2003, UAE, Dec. 2003, pp. 8-11, vol.1.
- Q. Khan, S. Wadhwa, K. Misri, “Low Power Startup Circuits for Voltage and Current Reference with zero steady state current,” International Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, August 2003, pp. 184-188.
- Q. Khan, S. Wadhwa, K. Misri, “A Low Voltage Switched-Capacitor Current Reference Circuit with low dependence on Process, Voltage and Temperature,” 16th International Conference on VLSI Design, New Delhi, India, Jan, 2003, pp. 504-506.

- N. Chandrachoodan, “Performance Analysis and Hierarchical Timing for DSP System Synthesis”, PhD thesis, Department of Electrical and Computer Engineering, University of Maryland, College Park, August 2002.
- N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. “High-level synthesis of DSP applications using adaptive negative cycle detection.”,
*EURASIP Journal on Applied Signal Processing*, 2002(9):893-907, September 2002. - S.Ramachandran and S.Srinivasan, “A fast FPGA-based MPEG-2 image encoder with a novel automatic quality control scheme” Elsevier Science, Microprocessors and Microsystems, Vol.25, pp. 449-457, 2002
- S. Ramachandran and S. Srinivasan, “A novel automatic quality control scheme for real time image transmission.” VLSI Design Journal, USA, Vol. 14(4), pp. 329-335, 2002
- S. Ramachandran and S. Srinivasan, A dynamically reconfigurable video compression scheme using FPGAs with coarse-grain parallelism”, VLSI Design Journal, USA Vol. 15(2), pp. 521-528, 2002.
- K. Seth and S. Srinivasan, “Data scheduling scheme for power reduction in DWT-based image coders”, Electronics Letters, Vol. 38, No.9, pp 408-409, April 2002.
- Kavish Seth and S.Srinivasan, “VLSI Implementation of 2-D DWT/IDWT Cores using 9/7 - tap filter banks based on the Non-expansive Symmetric Extension Scheme”, Fifteenth International Conference on VLSI Design, 2002.

- D. Frey, Y. Tsividis, G. Efthivoulidis, and N. Krishnapura, “Syllabic-companding Log Domain Filters”,
*IEEE Transactions on Circuits and Systems II*, vol 48, no. 4, pp. 329-339, Apr. 2001.(paper) - G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, “ A 165 Msps 8 bit CMOS A/D Converter with Background Offset Cancellation ”,
*Proceedings of the Custom Integrated Circuits Conference*, May 2001. (paper) - N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. “Adaptive negative cycle detection in dynamic graphs.”, In
*Proceedings of the International Symposium on Circuits and Systems*, pages V-163-V-166, Sydney, Australia, May 2001. - N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. “An efficient timing model for hardware implementation of multirate dataflow graphs.”, In
*Proceedings of the International Conference on Acoustics, Speech, and Signal Processing*, Salt Lake City, Utah, May 2001. - N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. “The hierarchical timing pair model.”, In
*Proceedings of the International Symposium on Circuits and Systems*, pages V-367-V-370, Sydney, Australia, May 2001. - N. Krishnapura and Y. Tsividis, “A Micropower Log-Domain Filter Using Enhanced Lateral PNPs in a 0.25um CMOS Process”,
*2001 VLSI Symposium on Circuits*, pp. 179-182, Jun. 16 2001, Kyoto, Japan.(paper, slides) - N. Krishnapura and Y. Tsividis, “Dynamically Biased 1MHz Low-pass Filter with 61dB peak SNR and 112dB Input Range”,
*IEEE International Solid State Circuits Conference*, pp. 360-361,465, slide supplement pp. 292-293,507, Feb. 4-7 2001, San Fransisco, USA.(paper, slides) - N. Krishnapura and Y. Tsividis, “Noise and Power Reduction in Filters Through the Use of Adjustable Biasing”,
*IEEE Journal of Solid State Circuits*, vol. 36, no. 12, pp. 1912-1920, Dec. 2001. (paper) - S.Ramachandran and S.Srinivasan, “FPGA Implementation of a Novel, Fast Motion Estimation Algorithm for Real-Time Video Compression.”, Ninth International Symposium on Field Programmable Gate Arrays , Monterey, California, USA, Feb., 2001

- K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process”,
*IEEE Journal of Solid State Circuits,*December 2000. - K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “ A 700 Msps 6 bit Read Channel A/D Converter with 7 bit Servo Mode”, International Solid State Circuits Conference, February 2000. (paper)
- K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “ A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS”, Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000.
- N. Krishnapura and P. Kinget, “A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS”, IEEE Journal of Solid State Circuits, vol. 35, no. 7, pp. 1019-1024, Jul. 2000. (paper)
- N. Krishnapura, Y. Tsividis, and D. R. Frey, “Simplified Technique for Syllabic Companding in Log-domain Filters”, Electronics Letters, vol. 36, no. 15, pp. 1257-1259, 20th Jul. 2000.(paper)
- S. Pavan and Y. Tsividis, “Time Scaled Electrical Networks - Properties and Applications in the Design of Programmable Analog Filters”, IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, , Vol. 47, No.2, pp. 161-5, February 2000.(paper)
- S. Pavan, Y. Tsividis and K. Nagaraj, “ Widely Programmable High Frequency Continuous Time Filters in Digital CMOS Technology”, IEEE Journal of Solid State Circuits,, Vol. 35, No.4, April 2000.(paper)
- Shrenik Patel and S.Srinivasan, “A modified EZW algorithm for fast implementation of a wavelet-based image codec”, accepted for publication in Electronics Letters, Vol. 36, No.20, pp. 1713-1714, 2000
- S.Ramachandran and S.Srinivasan, “A Programmable Pruning Level Control based MPEG Video Encoder”, International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland, May 2000.
- S.Ramachandran and S.Srinivasan, “Design and Implementation of an EPLD - based Variable Length Coder for Real Time Image Compression Applications”, International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland, May, 2000.

- N. Krishnapura and P. Kinget, “A 5.3 GHz Programmable Divider for HiPerLAN in 0.25um CMOS”, European Solid State Circuits Conference, pp. 144-147, Sep 21-23 1999, Duisburg, Germany. (paper, slides)
- S. Pavan, Y. Tsividis and K. Nagaraj, “ A 60-350 MHz Programmable Analog Filter in a Digital CMOS Process”, Proceedings of the European Solid State Circuits Conference,, September 21-23 1999, Duisburg, Germany.(paper, slides)
- S. Pavan, Y. Tsividis and K. Nagaraj, “Modeling of Accumulation MOS Capacitors for Analog Design in Digital VLSI Processes”, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, May 31-June 3 1999, Orlando, Florida.(paper, slides )
- D.V.R. Murthy, S. Ramachandran and S. Srinivasan, “ Parallel Implementation Of 2D-Discrete Cosine Transform Using ELPDs”, Twelfth International Conference on VLSI Design, Goa, Jan 1999.
- S.Ramachandran, S.Srinivasan and R.Chen, “EPLD-based Architecture of Real Time 2D-Discrete Cosine Transform and quantization for Image Compression”, International Symposium on Circuits and Systems (ISCAS '99), Orlando, Florida, May - June 1999.
- T.G.Venkatesh and S.Srinivasan, “A Pruning based fast rate control algorithm for MPEG coding”, Third International Conference on Computational Intelligence and Multimedia Applications (ICCIMA'99), New Delhi, Aug. 1999.

- L. Toth, Y. Tsividis, and N. Krishnapura, “Analysis of Noise and Interference in Companding Signal Processors”, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, Jun 1-3 1998, Monterey, California. (paper, slides)
- L. Toth, Y. Tsividis, and N. Krishnapura, “On the Analysis of Noise and Interference in Instantaneously Companding Signal Processors”, IEEE Transactions on Circuits and systems-II, vol. 45, no. 9, pp. 1242-1249, Sep. 1998. (paper)
- N. Krishnapura, S. Pavan, C. Mathiazhagan, and B. Ramamurthi, “A Baseband Pulse Shaping Method for Gaussian Minimum Shift Keying”, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 249-252, Jun 1-3 1998, Monterey, California. (paper, slides)
- N. Krishnapura, Y. Tsividis, K. Nagaraj, and K. Suyama, “Switched Capacitor Companding Filters”, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California. (paper, slides)
- S. Pavan and Y. Tsividis, “An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning”, IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California.(paper)
- S. Pavan and Y. Tsividis, “An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning”, IEEE Transactions on Circuits and Systems-I, vol. 45, no. 9, pp. 1242-1249, May 1998. (paper)
- S. Venkatesh and S. Srinvasan, “A Modified Butterfly Structure For Efficient Implementation Of Pruned Cosine Transform”, Electronics Letters, Vol. 34, No.14, pp. 1383-1385, July 1998
- S. Srinivasan and B. Srikanth, “Implementation Of A Fast Data Access Architecture For Two Dimensional Applications, International Conference on Computational Intelligence and Multimedia Applications, Churchill, Australia, Feb 1998.
- S. Venkatesh, S. Srinivasan and R.Chen. “An Efficient Implementation Of A Progressive Image Transmission System Using Successive Pruning Algorithm On A Parallel Architecture”, Intl. Conf. On High Performance Computing, Madras, India, Dec 1998.

- M. Bansal, Q. Khan, C. Shi, Average current mode control of multi-phase switching power converters, US 9,442,140, Sep. 13, 2016.
- Q. Khan, S. Dhar, J. Zazzera, T. Sutton, Circuits and Methods for Driving Resonant Actuators, US 9,344,022, May 17, 2016.
- Davinder Aggarwal, Vibhor Jain, Janakiraman VIRARAGHAVAN, “Automated design rule checking (DRC) test case generation”, US 8,875,064, Oct 28, 2014.
- Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh, Janakiraman VIRARAGHAVAN, “Generic design rule checking (DRC) test case extraction”, US 9,292,652, Mar 22 2016.
- C. Narathong and S. Aniruddhan, “Multi-mode Configurable Transmitter Circuit”, US 8,099,127, Jan. 17, 2012.
- C. Narathong, S. Aniruddhan and W. Su, “Amplifier with Gain Expansion Stage”, US 8,035,443, Oct. 11, 2011.
- B. Sun, S. Aniruddhan and S. Sridhara, “Method and Apparatus for Divider Unit Synchronization”, US 7,965,111, Jun. 25, 2011.
- S. Aniruddhan, B. Sun, A. Jayaraman and G.S. Sahota, “Mixer with High Output Power Accuracy and Low Local Oscillator Leakage”, US 7,941,115, May 10, 2011.
- C. Narathong and S. Aniruddhan, “Techniques for improving Balun Loaded-Q”, US 7,863,986, Jan. 4, 2011.
- Q. Khan, S. Wadhwa, D. Tripathi, G.K. Sidhartha, K. Misri, PVT Variation Detection and Compensation Circuit, US 7495465, Feb. 24, 2009.
- D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri, S. Wadhwa, US 7446592, PVT Variation Detection and Compensation Circuit, Nov. 4, 2008.
- Q. Khan, G.K. Sidhartha, Sequence-independent Power-on Reset for Multi-Voltage Circuits, US 7432748, Oct. 7, 2008.
- D. Tripathi, J. Banerjee, Q. Khan, Differential Receiver Circuit, US 7414462, Aug. 19, 2008.
- Q. Khan, H. Fukazawa, T. Nandurkar, Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit, US 7388422, Jun. 17, 2008.
- G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa, K. Misri, PVT Variation Detection and Compensation Circuit, US 7388419, Jun. 17, 2008.
- N. Krishnapura(with I. Shpantzer et al.), “System and method for code division multiplexed optical communication”, US 7,167,651, Jan. 23, 2007.
- Q. Khan, D. Tripathi, Transmission Line Driver Circuit, US 7292073, Nov. 6, 2007.
- D. Tripathi, Q. Khan, K. Misri, Transmission Line Driver, US 7187197, Mar. 6, 2007.
- S. Wadhwa, Q. Khan, K. Misri, D. Muhury, Digital Clock Frequency Doubler, US 7132863, Nov. 7, 2006.
- Q. Khan, D. Tripathi, K. Misri, High Voltage Level Converter Using Low Voltage Devices, US 7102410, Sep. 5, 2006.
- Q. Khan, S. Wadhwa, K. Misri, Bandgap Reference Circuit, US 7084698, Aug. 1, 2006.
- Q. Khan, S. Wadhwa, K. Misri, Bidirectional Level Shifter, US 7061299, Jun, 13, 2006.
- Q. Khan, S. Wadhwa, K. Misri, Single Supply Level Shifter, US 7009424, Mar. 7, 2006.
- Shanthi Pavan, “Integrated circuit implementation for power and area efficient adaptive equalization”, US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California.
- N. Krishnapura(with I. Shpantzer et al.), “System and method for orthogonal frequency division multiplexed optical communication”, US 7,076,169, Jul. 11, 2006.
- John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao, “Method and apparatus for improved high-speed adaptive equalization”, US 7,003,228, Feb. 21, 2006.
- Shanthi Pavan et al., “Mobility Compensation in MOS Integrated Circuits”, US 6,822,505, 23 Nov. 2004.
- N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,816,003, Nov. 9, 2004.
- N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,717,461, Apr. 6, 2004.
- N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,683,492, Jan. 27, 2004.
- P. Kinget and N. Krishnapura, “Glitch Free Phase Switching Synthesizer”, US 6,671,341, Dec. 30, 2003.
- Shanthi Pavan et al., “Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier”, US 6,552,615, 22 Apr. 2003.
- Shanthi Pavan et al., “Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells”, US 6,545,567, 8 Apr. 2003.
- Shanthi Pavan, “Fixed Transconductance Bias Apparatus”, US 6,400,185, 4 Jun. 2002.
- Shanthi Pavan et al., “Fast Acting Polarity Detector”, US 6,369,726, 2 Apr. 2002.
- Shanthi Pavan, “Low Distortion Sample-and-Hold Circuit”, US 6,323,697, 27 Nov. 2001.
- Shanthi Pavan, “High Frequency Boost Technique”, US 6,304,134, 16 Oct. 2001
- P. Kinget and N. Krishnapura, “Programmable Frequency Divider”, US 6,281,721, Aug. 28, 2001.
- Shanthi Pavan et al., “Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation”, US 5,945,889, 31 Aug. 1999.