EE6331: Embedded Memory Design (Jan 2021)

• Janakiraman Viraraghavan (IITM)
• Dr. Rahul Rao (STSM IBM. India. Pvt. Ltd, Adjunct Faculty IITM)

Online - Flipped Classroom Mode

Live session: S-slot - Thu (2:00 - 3:00 PM)

• Weekly Quiz: 20%
• Mid Term: 30%
• Project : 20%
• End Semester Exam: 30%

(Why we teach this course?)

• Introduce students to some relevant advanced topics of current interest in academia and industry
• Give the students a feel for research topics
• Make students aware of work happening in industries, specifically in India

This course will cover three broad subjects:

1. SRAM design (Rahul Rao)
2. Embedded DRAM design (Janakiraman)
3. Non-Volatile Memories (Janakiraman)

(What the students should be able to do after the course)

• Explain the working of a(n) (e)DRAM and what Embedded means?
• Explain the working of a feedback sense amplifier and modify existing designs to improve performance
• Calculate the voltage levels of operation of various components for an eDRAM
• Introduce stacked protect devices to reduce voltage stress of the WL driver

• Articulate memory hierarchy and the value proposition of SRAMs in the memory chain + utilization in current processors
• Explain SRAM building blocks and peripheral operations and memory architecture (with physical arrangement)
• Articulate commonly used SRAM cells (6T vs 8T), their advantages and disadvantages
• Explain the operation of a non-conventional SRAM cells, and their limitations
• Explain commonly used assist methods
• Explain how variations impact memory cells

• Basics of DRAM
• Definition of Embedded
• Requirement for short BLs in DRAMs
• Transfer ratio
• Retention time/ Refresh rate analysis
• Power supplies required for eDRAM
• Advantages of eDRAM over eSRAM

Lecture Slides

• Write time calculation
• Hierarchical sensing
• 3T Micro Sense Amp
• 3T Micro Sense Amp Noise Analysis

Barth, J. et al., “A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008. PDF

Lecture Slides

• 3T Micro Sense Amp - Evolution
• 3T Micro Sense Amp - GSA
• 3T Micro Sense Amp - DSA
• Read Time Analysis
• SOI Technology Problems

Lecture Slides

Gated Feedback Sense Amplifier

• Construction
• Read and Refresh
• Read Data Mux
• Write

G. Fredeman et al., “A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. doi: 10.1109/JSSC.2015.2456873 PDF

Lecture Slides

• Variability study
• Thick Oxide Word-line drivers
• Thin Oxide Word-line drivers
• Memory Testing

Consolidated Lecture Slides

• Introduction to Non-Volatile Memory
• Charge Trap Transistors
• Multi Time Programmable CTT
• Circuit Design Details

• Memory hierarchy
• Memory organization
• Flip flop
• 6T SRAM basics

• 6T SRAM cell
• Static/ Read and Write noise margins
• Read/ Write/ Hold and Access failures

Lecture Slides

• Memory Arrangement
• Alternative Cell Types
• Column interleaving
• Memory Folding

Lecture Slides

• 8T SRAM Cell
• Multi-port SRAM
• Variations
• Redundancy

Lecture Slides

• Redundancy
• Assist Circuits
• Multi VCC SRAM cells
• Bias Temperature Instability

Lecture Slides

• BTI Failure
• Hot Carrier Injection
• Power
• Fault Testing

Lecture Slides

• Variation Characterization
• Array-Based IV characterization
• Digital Characterization

Lecture Slides

• Variation Characterization
• Critical Path Monitor
• SRAM Fluctuation Monitor

Lecture Slides