Papers I have (co-)authored

Approximate Computing and Neural Networks
  1. K.B.N.Girish, Nitin Chandrachoodan and Vinita Vasudevan, " A smoothed LASSO based DNN Sparsification Technique", IEEE Trans. Circuits and Syatems, 68-10, Oct. 2021
  2. K.B.N.Girish and V.Vasudevan, "Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization. IEEE Trans. on Circuits and Systems 66-II(5): 848-852, 2019
  3. D.Celia, Vinita Vasudevan and Nitin Chandrachoodan, "Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders", IET Computers and Digital Techniques, vol 15, 2021, pp97-111.
  4. D.Celia, Vinita Vasudevan and Nitin Chandrachoodan, "Optimization of signal processing applications using parameterized error models for approximate adders", ACM Trans. Embedded Computing Systems, Vol. 20, no. 2, March 2021
  5. D Celia, Vinita Vasudevan and Nitin Chandrachoodan, "Optimizing power-accuracy trade-off in approximate adders", Proc. DATE, March 2018
  6. D Celia, Vinita Vasudevan and Nitin Chandrachoodan, "Probabilistic Error Modelling for two-part segmented Approximate Adders", Proc. ISCAS , May 2018
Reduced order modelling and SVD computation
  1. V.Charumathi, M.Ramakrishna and V.Vasudevan, "Fast Proper Orthogonal Decomposition Using Improved Sampling and Iterative Techniques for Singular Value Decomposition. arXiv:1905.05107 (2019) (Accepted for publication in ACM TOMS)
  2. V.Vasudevan and M.Ramakrishna, "An Efficient Algorithm for Frequency-Weighted Balanced Truncation of VLSI Interconnects in descriptor form", Proc. Des. Automation Conf., 2015 (pdf)
  3. Vinita Vasudevan and M.Ramakrishna, "A Hierarchical Singular Value Decomposition Algorithm for Low Rank Matrices. arXiv:1710.02812 (2017)
Statistical timing analysis
  1. P.R.Chithira and V.Vasudevan, " Potential Critical Path Selection based on a Time-Varying Statistical Timing Analysis Framework", IEEE Trans. VLSI systems, vol. 27, no. 6, June 2019 (pdf)
  2. P.R.Chithira and V.Vasudevan, "A Hierarchical Technique for statistical path selection and critcality computation", ACM Trans. Des. Automation of Electronic Systems (TODAES), vol 23, no. 1, Oct 2017 (pdf)
  3. S.Ramprasath and V.Vasudevan, "Efficient algorithms for discrete gate sizing and threshold voltage assignment based on an accurate analytical statistical yield gradient", ACM Trans. Des. Automation of Elecronic Systems (TODAES), vol. 21, no.4, May 2016 (pdf)
  4. S.Ramprasath, M.Vijaykumar and V.Vasudevan, "A skew-normal canonical model for statistical static timing analysis", IEEE Trans. VLSI systems, vol 24(6), pp 2359-68, June 2016 (pdf)
  5. S.Ramprasath and V.Vasudevan, " An efficient algorithm for statistical timing yield optimization", Proc. Design Automation Conf., 2015
  6. S.Ramprasath and V.Vasudevan, "Statistical criticality computation using circuit delay", IEEE Trans. Comput. Des. Int. ciruits and systems, vol 33(5), pp 717-727, 2014
  7. M.Vijaykumar and V.Vasudevan, "Statistical static timing analysis using a skew-normal canonical delay model", Proc. of design automation and test (DATE) 2014,
  8. S.Ramprasath and V.Vasudevan, "On the computation of criticality in statistical static timing analysis", ICCAD, Nov. 2012, pp 172-79. (pdf)
  1. V.Vasudevan, "Analysis of clock jitter in continuous-time sigma-delta converters", IEEE Trans. Circuits and Systems-I, vol 56(3), pp 519-528, March 2009 (pdf)
  2. V.Vasudevan, "Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits",Proc. $42^{nd}$ Design Automation Conference, pp 397-442, June 2005.
  3. V.Vasudevan "A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory", IEEE Trans. Circuits and Systems-I:Regular papers, vol.51(11), pp 2174-2178, Nov. 2004
  4. V.Vasudevan and M.Ramakrishna "Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits", IEEE Trans. Circuits and Systems-I:Regular papers, vol.51(11), pp 2165-2174, Nov 2004 (pdf)
  5. V.Vasudevan "A Time-Domain Technique for Computation of Noise Spectral Density in Linear and Non-Linear Time-Varying Circuits" IEEE Trans. Circuits and Systems-I, vol 51(2), pp422,433, Feb 2004. (pdf)
  6. V.Vasudevan, "A Time-Domain Technique for Computation of Noise Spectral Density in Switched Capacitor Circuits", Proc.of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Vol 1., pp 585-588.
  7. V.Vasudevan and M.Ramakrishna, "Computation of Noise Spectral Density in Switched Capacitor Circuits using the Mixed-Frequency-Time Technique", Proc. Design Automation Conference, June 2003
Mixed-signal BIST
  1. K.P.Sunil Rafeeque and V.Vasudevan, "A New Technique for on-chip error estimation and reconfiguration of current steering digital to analog converters'', IEEE Trans. Circuits and Systems-I:Regular papers, Nov. 2005. (pdf)
  2. K.P. Sunil Rafeeque and V.Vasudevan, ``A Built-In-Self-Test Scheme for Segmented and Binary Weighted DACs'', Journal of Electronic Testing:Theory and Applications, vol. 20, pp 623-638, Dec. 2004
  3. K.P.Sunil Rafeeque and V.Vasudevan, ``An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC'', Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04'', vol. 1, pp 281-284, May, 2004
  4. K.P.S.Rafeeque and V.Vasudevan, "A Built-in-Self-Test scheme for Digital to Analog Converters", Proc. 17th International Conference on VLSI design, pp1027-1032, 2004.
Digital design
  1. K.N.Vikram and V.Vasudevan, ``Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures'', IEEE Trans. VLSI design, Sept. 2006. (pdf)
  2. K.N. Vikram and V. Vasudevan, Scheduling divisible loads on partially reconfigurable hardware, Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, Poster Summary, April 2006. (pdf)
  3. K.N.Vikram, V.Vasudevan and S.Srinivasan, ``Rate-distortion estimation for fast JPEG2000 compression at low bit-rates'', Electronics letters, vol. 41(1), pp16-18, Jan. 2006
  4. K.N.Vikram and V.Vasudevan, ``Hardware-software co-simulation of bus-based reconfigurable systems'', Microprocessors and Microsystems, vol. 29(4), pp 133-144, May 2005.
Papers in CAD/design/devices
  1. Rajesh T.N.Rajaram and V.Vasudevan, "Optimisation of the one-dimensional full search algorithm and implementation using an EPLD", Proceedings of the 13th International conference on VLSI design, pp 336-341, 2000.
  2. T.Pramod, R.K.Dash, V.Vasudevan and M.Ramakrishna, "A Transistor level Placement tool for custom cell generation", Proceedings of the 13th International Conference on VLSI Design, pp 254-257, Jan. 2000.
  3. P.Gopalakrishnan and V.Vasudevan, "A modified line expansion algorithm for device level routing of analog integrated circuits", Proeedings of the 11th International conference in VLSI design pp 265-268, 1998.
  4. C.F.Prince and V.Vasudevan, "Symbolic analysis of Analog Integrated circuits", Proceedings of the 11th International conference in VLSI design, pp 167-173, 1998.
  5. K.Ravi Shanker and V.Vasudevan, "Synthesis of Analog CMOS circuits", Proceedings of the 10th Internation conference in VLSI Design, pp439-445, 1997.
  6. Shehanaj N. Begum, E.Bhattacharya and V.Vasudevan, "Measurement and optimisation of DC Gummel-Poon model parameters for the Bipolar Junction Transistors", Proceedings of the International workshop on physics of semiconductor devices, New Delhi, Dec. 1999, vol.1, pp558-561.
  7. V.Vasudevan and J.Vasi, "A Two-dimensional simulation of Radiation effects in MOS transistors", IEEE Trans. Electron. Devices, vol.41(3), pp 381-386, 1994.
  8. V.Vasudevan and J.Vasi, "A simulation of the multiple trapping model for CTRW transport, J.Appl. Phys.", vol. 74, p.3224, 1992.
  9. V.Vasudevan and J.Vasi, "A Numerical simulation of Hole and Electron Trapping due to Radiation in Silicon Dioxide", Journal of Appl. Phys, vol.70, pp 4490, 1991.