• Janakiraman Viraraghavan (IITM)

• CS-25

• G-slot
• M(12:00-12:50 PM)
• Th(10:00-10:50 AM)
• F(09:00-09:50 PM)

• W (4:00 - 5:40 PM) @ ESB-127

• Assignments: 10%
• Quiz 1: 15%
• Quiz 2: 15%
• End Semester Exam: 40%
• Project - 20%

• Model File (22nm PTM File): Download

All lecture notes available here are based on the following text books.

• Digital Integrated Circuits Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice Hall India
• CMOS VLSI Design, Neil H.E. Weste, David Harris and Ayan Banerjee, 3rd Edition, Pearson Education

Module 6 (Adders and Multipliers) alone uses some extra material from

• Prof. Vinita Vasudevan's lecture notes on adders and multipliers [http://www.ee.iitm.ac.in/vinita/digic.html]

(What the students should be able to do after the course)

• Characterize the key delay quantities of a standard cell
• Evaluate power dissipated in a circuit (dynamic and leakage)
• Design a circuit to perform a certain functionality with specified speed
• Identify the critical path of a combinational circuit
• Convert the combinational block to pipelined circuit
• Calculate the maximum (worst case) operating frequency of the designed circuit

• Motivation
• Chip design complexity
• Design Flow

Lecture Slides

Learning Objectives:

1. Explain short channel effects(SCE) like Drain Induced Barrier Lowering, Gate Induced Drain Leakage, Sub-threshold leakage, Channel length modulation
2. Derive the equation for ON current of a CMOS transistor with first order SC
3. Estimate various capacitance values for a transistor
4. Estimate the equivalent ON resistance of a transistor

Contents:

1. Silicon and Doping
2. P-N Junction
3. CMOS Transistor

• Threshold Voltage
• ON Current
• Channel length modulation
• Velocity saturation
• Sub-threshold leakage
• Drain Induced Barrier Leakage
• Gate Induced Drain leakage
• (Reverse) Short Channel Effect
• Other leakage mechanisms
• Capacitance
• Resistance

Lecture Slides

Learning Objectives:

1. Estimate the wire parasitics given the sheet resistance and the capacitance per unit length
2. Derive the Elmore delay for a given RC tree
3. Estimate the wire RC delay by applying the Elmore delay model to a distributed RC network

Contents:

1. Capacitance
2. Resistance
3. Sheet Resistance
4. Skin depth
5. Resistance Models
6. Lumped model (C and RC)
7. Propagating delay and rise time
8. Elmore delay model
9. Example - Time constant of a rc-wire model

Lecture Slides