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EE5311: Digital IC Design (Aug-Nov 2019)
Instructors
Classroom
Schedule
G-slot
M(12:00-12:50 PM)
Th(10:00-10:50 AM)
F(09:00-09:50 PM)
Extended Tutorial
Evaluation
Assignments: 10%
Quiz 1: 15%
Quiz 2: 15%
End Semester Exam: 40%
Project - 20%
Simulation
Reference Text Books
All lecture notes available here are based on the following text books.
Digital Integrated Circuits Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice Hall India
CMOS VLSI Design, Neil H.E. Weste, David Harris and Ayan Banerjee, 3rd Edition, Pearson Education
Module 6 (Adders and Multipliers) alone uses some extra material from
Learning Objectives
(What the students should be able to do after the course)
Characterize the key delay quantities of a standard cell
Evaluate power dissipated in a circuit (dynamic and leakage)
Design a circuit to perform a certain functionality with specified speed
Identify the critical path of a combinational circuit
Convert the combinational block to pipelined circuit
Calculate the maximum (worst case) operating frequency of the designed circuit
Module-0 - Introduction
Module-1 - The Transistor
Learning Objectives:
Explain short channel effects(SCE) like Drain Induced Barrier Lowering, Gate Induced Drain Leakage, Sub-threshold leakage, Channel length modulation
Derive the equation for ON current of a CMOS transistor with first order SC
Estimate various capacitance values for a transistor
Estimate the equivalent ON resistance of a transistor
Contents:
Silicon and Doping
P-N Junction
CMOS Transistor
Threshold Voltage
ON Current
Channel length modulation
Velocity saturation
Sub-threshold leakage
Drain Induced Barrier Leakage
Gate Induced Drain leakage
(Reverse) Short Channel Effect
Other leakage mechanisms
Capacitance
Resistance
Lecture Slides