• Shanthi Pavan

• Web Studio - 2 , ICSR

Monday 3-5pm, Other 2 hours TBD

• TBD

There will be assignments approximately every two weeks. These will count for 60% of the grade and the end semester exam for the remaining 40%.

Knowledge of MOS transistor basics related to circuit design, small signal equivalent circuits, small and large signal analysis; Design of building blocks-opamps, bias generators, amplifier stages, basics of continuous-time and discrete-time signals

This course deals with A/D and D/A conversion systems.

Topics: Sampling and quantization in time and frequency domains; Reduction of quantization noise by oversampling and noise shaping; Discrete-time and Continuous-time Delta Sigma modulators; Flash A/D converter-Sample and hold circuits, preamplifiers and latches; D/A converter-Current Steering, Resistor array and Switched capacitor array; Static nonidealities of A/D and D/A converters due to component mismatch; Multi step Flash A/D converter;

you can see Lectures (2008) . You need to register for access.

Assignments will be posted below. You are expected to solve them on your own. You can approach the teaching assistants for clarifications and help. Only electronic submission is allowed. Submissions beyond the due date will receive zero credit. Please Email the assignments ONLY to ee658.iitm@gmail.com

Information on simulators and device models are available here.

• Problem Set 1, due Jan 30
• Problem Set 2, due Feb 14
• Problem Set 3, due Feb 28
• Problem Set 4, due Mar 24
• Problem Set 5, due Apr 14

Listed below are some references. There is also a host of information available on the WWW - especially in application notes of Analog Devices.

1. CMOS Data Converters for Communication - M. Gustavsson, J. Wikner, and N. Tan. Kluwer Academic Publishers, 2000.Here is a link to the review of the book.
2. Principles of Data Conversion System Design - Behzad Razavi.
3. The IEEE Journal of Solid State Circuits (JSSC) is the best place to look for information on state of the art data converter implementations. Within the IIT Campus, it can be accessed online through IEEEXplore

Listed below are links to papers you can read to gain further intuition, or reinforce your knowledge gained in the lectures.

1. Time interleaved converter arrays W.C.Black and D.A. Hodges, IEEE Journal of Solid-State Circuits, December 1980.
2. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter A. Abo and P. Gray, IEEE Journal of Solid-State Circuits, May 1999.(Look at Fig.7 and the corresponding description for a slight variant of the bootstrap switch done in class.)
3. Chapter 12 in Design of Analog CMOS Integrated Circuits - Behzad Razavi, Tata McGraw Hill Publishers, for a good introduction to switched-capacitor circuits.
4. ADC and DAC glossary from Maxim.
5. vlsi_data_conv_notes.pdf

1. K. Nagaraj, D. A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. R. Viswanathan, “A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit a/d converter in a 0.25-µm digital CMOS process,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1760 - 1768, December 2000. Discusses bootstrapped sample and hold, interleaved S/H, preamplifiers with offset correction.
2. C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 184 - 191, February 1990. Discusses latch design, error correction using majority encoding.
3. V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar, “ A Distortion Compensating Flash Analog to Digital Conversion Technique,” IEEE Journal of Solid State Circuits. September 2006. (paper)
4. J. Lin and B. Haroun, “An embedded 0.8 V/480 µW 6B/22 MHz flash ADC in 0.13-µm digital CMOS Process using a nonlinear double interpolation technique,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1610 - 1617, December 2002.
5. M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D converter in 0.35-µm CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 1847 - 1858, December 2001.
6. R. Sarpeshkar, J. Wyatt and N. Lu, “Mismatch sensitivity of a simultaneously latched CMOS sense amplifier”, IEEE Journal of Solid State Circuits, 1991. (paper) - analysis of dynamic mismatch in a latch.

1. Delta-Sigma Data Converters: Theory, Design, and Simulation - by Steven R. Norsworthy, Richard Schreier, Gabor C. Temes (the Yellow Bible of Delta-Sigma Converters)
2. Understanding Delta-Sigma Data Converters - by Richard Schreier, Gabor C. Temes (the Green Bible of Delta-Sigma Converters)
3. Theory, Practice, and Fundamental Performance Limits of High-Speed Data Conversion Using Continuous-Time Delta-Sigma Modulators. PhD Dissertation, James A Cherry Thesis.Excellent discussion of continuous-time delta-sigma conversion.A must read for anybody serious about CTDSMs.
4. J. De La Rosa, “Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey,” IEEE Transactions on Circuits and Systems : Regular Papers, January 2011. (paper)
5. S. Pavan, “Efficient simulation of weak nonlinearities in continuous-time oversampling converters”, IEEE Transactions on Circuits and Systems : Regular Papers, August 2010. (paper)
6. S. Pavan and P. Sankar, “Power reduction in continuous-time Delta-Sigma Modulators using the assisted opamp technique”, IEEE Journal of Solid State Circuits, July 2010. (paper) (most read paper in the IEEE Journal of Solid State Circuits in July 2010, and 11th most downloaded paper from ALL of IEEEXplore in July 2010)link
7. S. Pavan, “Systematic design centering of continuous-time oversampling converters”, IEEE Transactions on Circuits and Systems : Express Briefs, March 2010 (paper)
8. S.Pavan, “Excess Loop Delay Compensation in Continuous-time Delta Sigma Modulators”, IEEE Transactions on Circuits and Systems II : Express Briefs, November 2008.(paper)
9. K. Reddy and S. Pavan, “Fundamental Limitations of Continuous-time Delta Sigma Modulators due to Clock Jitter”, IEEE Transactions on Circuits and Systems : Regular Papers, October 2007.(paper)
10. S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, “A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications,” IEEE Journal of Solid State Circuits, February 2008.(paper)

• A collection of latches from the IEEE Journal of Solid State Circuits. Go through the circuits and see how they work and compare them. Read the authors thought processes in the complete articles.

• Douglas Mercer; “A study of error sources in current steering digital-to-analog converters”, 2004 IEEE Custom Integrated Circuits Conference, May 2004. A very good summary of error sources in current steering D/A converters
• Chi-Hung Lin, Klaas Bult; “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2”, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948 - 1958, December 1998. An extremely well designed DAC which holds its performance up to the nyquist frequency. A very well made DAC IC
• Bernd Schafferer, Richard Adams; “A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications”, IEEE International Solid-State Circuits Conference, vol. XVII, pp. 360 - 361, February 2004. More recent, more resolution; Has techniques to make tail node jumps independent of signal
• Yonghua Cong, Randall L. Geiger; “A 1.5-V 14-bit 100-MS/s self-calibrated DAC”, IEEE Journal of Solid-State Circuits, vol. 38, pp. 2051 - 2060, December 2003. Discusses optimization of switching sequence
• D. Wouter J. Groeneveld, Hans J. Schouwenaars, Henk A. H. Termeer, Cornelis A. A. Bastiaansen; “A self-calibration technique for monolithic high-resolution D/A converters”, IEEE Journal of Solid-State Circuits, vol. 24, pp. 1517 - 1522, December 1989. Calibrated current steering DAC
• Jurgen Deveugele, Michiel Steyaert; “A 10b 250MS/s binary-weighted current-steering DAC”, IEEE International Solid-State Circuits Conference, vol. XVII, pp. 362 - 363, February 2004. Discusses use of full binary weighting as opposed to thermometer MSBs