# EE5311: Digital IC Design

## Schedule

G Slot

• M (12:00 - 12:50)
• W (16:50 - 17:40) - Tutorial hour
• Th (10:00 - 11:00)
• F (9:00 - 10:00)

## Weekly Quiz

Students will take a quiz on Moodle every week in one of the G slot hours.

## TA Contact Hour

Students can contact the TA for questions and doubts in tools and other aspect of the course in one of the G-slot hours.

## Evaluation

• Assignments:
• Weekly Quizzes:
• Mid Sem:
• End Semester Exam:
• Project:

## Reference Text Books

All lecture notes available here are based on the following text books.

• Digital Integrated Circuits Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice Hall India
• CMOS VLSI Design, Neil H.E. Weste, David Harris and Ayan Banerjee, 3rd Edition, Pearson Education

Module 6 (Adders and Multipliers) alone uses some extra material from

## Learning Objectives

(What the students should be able to do after the course)

• Characterize the key delay quantities of a standard cell
• Evaluate power dissipated in a circuit (dynamic and leakage)
• Design a circuit to perform a certain functionality with specified speed
• Identify the critical path of a combinational circuit
• Convert the combinational block to pipelined circuit
• Calculate the maximum (worst case) operating frequency of the designed circuit

## Module-0 - Introduction

• Motivation
• Chip design complexity
• Design Flow

## Module-1 - The Transistor

Learning Objectives:

1. Explain short channel effects(SCE) like Drain Induced Barrier Lowering, Gate Induced Drain Leakage, Sub-threshold leakage, Channel length modulation
2. Derive the equation for ON current of a CMOS transistor with first order SC
3. Estimate various capacitance values for a transistor
4. Estimate the equivalent ON resistance of a transistor

Contents:

1. Silicon and Doping
2. P-N Junction
3. CMOS Transistor
• Threshold Voltage
• ON Current
• Channel length modulation
• Velocity saturation
• Sub-threshold leakage
• Drain Induced Barrier Leakage
• Gate Induced Drain leakage
• (Reverse) Short Channel Effect
• Other leakage mechanisms
• Capacitance
• Resistance

## Module-2 - Interconnects

Learning Objectives:

1. Estimate the wire parasitics given the sheet resistance and the capacitance per unit length
2. Derive the Elmore delay for a given RC tree
3. Estimate the wire RC delay by applying the Elmore delay model to a distributed RC network

Contents:

1. Capacitance
2. Resistance
3. Sheet Resistance
4. Skin depth
5. Resistance Models
6. Lumped model (C and RC)
7. Propagating delay and rise time
8. Elmore delay model
9. Example - Time constant of a rc-wire model

## Module-3 - The Inverter

Learning Objectives:

1. Explain the functioning of a CMOS inverter
2. Explain the Voltage Transfer Characteristics of an inverter
3. Derive an expression for the trip point of an inverter
4. Derive an expression for the delay of an inverter driving a load
5. Derive expressions for Static, Dynamic and Short Circuit power of an inverter.

Contents:

1. Switch Model
2. Transfer Characteristics
3. Switching Threshold
4. Noise Margin
5. Supply Voltage Scaling
6. Propagation Delay
7. Power
1. Dynamic
2. Short circuit
3. Leakage

## Module-4 - Combinational Circuit Design

Learning Objectives:

1. Explain logical effort (LE) and electrical effort (EE)
2. Derive the optimum number of buffers with their sizes to drive a load.
3. Implement any arbitrary boolean function in Static CMOS logic
4. Derive logical effort for any gate built in any style of logic
5. Optimize the path delay of arbitrary gates driving a load capacitance
6. Implement logic functions using ratio'd logic and dynamic logic
7. Use the pass transistor to implement simple gates like MUX and XORs 8. Explain basic domino logic

Contents:

1. CMOS gates
2. Gate sizing
3. Capacitance estimation
4. Delay estimation
5. Logical effort
6. Path delay optimizaion
7. Buffer insertion
8. Circuit Families
1. Static CMOS
2. Ratioed gates
3. Cascode Voltage Switch Logic (CVSL) & Level Translators
4. Dynamic circuits
5. Pass Transistor circuits

## Module-5 - Sequential Circuits

Learning Objectives:

1. Build elementary sequential circuits like latches and flip flops - Static and Dynamic
2. Identify devices that affect set up and hold time
3. Derive max and min delay constraints for latch/ flip flop based pipeline systems
4. Account for clock skew in a pipelined system
5. Analyze time borrowing across half cycles and across cycles
6. Calculate the maximum clock frequency of operation of a pipelined system

Contents:

1. Sequencing Elements
2. Sequencing Methods
1. Flip flop
2. Latch
3. Delay definitions
4. Circuit Implementations of Latch/ Flop
1. Static
2. Dynamic
5. Max delay constraints
6. Min delay constraints
7. Time Borrowing

## Module-6 - Adders and Multipliers

Learning Objectives:

1. Design a full adder with least PMOS stack size using self duality principle
2. Construct adder architectures to reduce delay from O(N) to O(\sqrt{N}) - O(log(N))
3. Draw timing diagrams to show the signal propagation of various adders
4. Design an array multiplier for both signed and unsigned multiplication
5. Optimize the arrary multiplier using the inverting property of a Full Adder
6. Derive the Modified Booth Encoding to reduce the number of partial products
7. Design and implement a multipler based on the Modified Booth Encoding algorithm

Contents:

1. Basic terminology
2. Full adder circuit design 