Integrated Circuits and Systems group, IIT Madras

M.S. Theses guided

  1. G. Kumar 1983
  2. K. Elango 1985
  3. Parallel Implementation of JPEG Compression using Dual Processors. N.L. Vishvanathan, June 1995. Abstract
  4. Design and Development of a DSP based System for Acquisition and Analysis of EMG Signals. (Jointly with Dr. K.M. Patil , Department of Applied Mechanics, IIT Madras) G.Vijaya Krishna Prasad, Oct. 1995. Abstract
  5. VLSI Architectures for Pipelined IIR - Filters. R. Krishnan, Nov. 1996. Abstract
  6. Design and Development of Commercially viable ISDN Customer Premises Equipment. P. Samar, Sep. 1997.Abstract
  7. Design and Implementation of a Two Dimensional Data Access Architecture for Digital Signal Processors. (Jointly with Dr. Vinita Vasudevan, Department of Electrical Engg., IIT Madras) B. Srikanth, June 1998. Abstract
  8. Design and Development of a Bare Printed Circuit Board Diagnostic System via CAD Netlist Processing Algorithm. (Jointly with Dr C.Eswaran, Department of Electrical Engineering, IIT Madras) Ram Y. Gopal, July 1998. Abstract
  9. Design and Implementation of an Efficient Progressive Image Transmission System using Pruning Algorithms and a Parallel Architecture. S.Venkatesh, Aug. 1998. Abstract
  10. Fast Implementation of Motion Picture Compression Algorithms using a Pipelined Architecture with Embedded Bitrate Control. T.G. Venkatesh, Mar. 1999. Abstract
  11. Optimization of Fast Search Block Matching Motion Estimation Algorithms and their VLSI Implementation. (Jointly with Dr. Vinita Vasudevan, Department of Electrical Engg., IIT Madras) Rajesh T.N. Rajaram, June 1999. Abstract
  12. Time - Frequency Representations: Analysis and Implementation. (Jointly with Dr K.M.M. Prabhu, Department of Electrical Engineering, IIT Madras) Soma Sekhar Dhavala, Mar. 2000. Abstract
  13. Low Power ASIC Implementation of a Two-dimensional Discrete Wavelet Transform CODEC for Still Image Processing. (Jointly with Dr. S. Karmalkar, Department of Electrical Engineering, IIT Madras) Kavish Seth, Feb. 2002. Abstract
  14. A new video segmentation scheme for MPEG-4 applications: algorithm, architecture and implementation. A. Durga Kishore, Dec. 2002. Abstract
  15. Algorithms and Architectural Design of an Onboard Satellite QPSK Receiver. Sanjeev Dua, May 2003. Abstract
  16. Efficient architectures for Lifting based forward and inverse Discrete Wavelet Transforms for still image compression. Srikar Movva, Jan. 2004. Abstract
  17. Algorithmic implementation and architectural design of a modified Watershed Algorithm for image segmentation applications. Kumud Prakash Gupta, Mar. 2004. Abstract
  18. Design and Implementation of a novel FPGA based JPEG 2000 Codec. J. Sateesh Reddy, March 2006. Abstract
  19. G. Kannan - (Jointly with Dr. Nitin Chandrachoodan, Electrical Engineering Department, IIT Madras) (Ongoing)