By J. Sateesh Reddy

Keywords: JPEG2000, DWTQ, BPC, BAC, Bit-stream Organization

JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. To address these needs in the real time application of still image coding, system-level hardware architectures capable of encoding and decoding the JPEG 2000 core algorithm are designed, which uses discrete wavelet transform and quantization (DWTQ), intra-subband bit-plane coding (BPC), binary arithmetic coding (BAC) and bitstream organization as well as the inverse processing modules at the decoder end.

The architectures designed in the present work process an image as a tile by partitioning it into cells of smaller size. A cell size of 33×33 pixels for DWTQ and code block size of 16×16 coefficients for BPC were selected after analyzing the memory requirements, processing speed and quality of the reconstructed images. These sizes reduced the memory requirements appreciably without sacrificing the image quality. Although, quality is better in the case of still higher cell sizes, both the internal and external memory requirements are huge. This is especially important since we need to implement the Codec on an FPGA.

In the present work, novel architectures were developed for bitplane coder and binary arithmetic coder for the concurrent processing of three passes of a bitplane. The hardware architectures of JPEG 2000 Codec realized using Verilog are capable of compressing raw image from a camera at the encoder end and reconstruct the image at the decoder end.