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courses:ee5311_2019 [2019/08/23 06:25] janakiraman |
courses:ee5311_2019 [2019/10/14 11:38] janakiraman |
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| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-1/ee5311-module-1-transistor.pdf|Lecture Slides]] | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-1/ee5311-module-1-transistor.pdf|Lecture Slides]] | ||
| + | |||
| + | ===== Tutorial-1 - The Transistor ===== | ||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/tutorials/ee5311-tut-1.pdf|Tutorial-1]] | ||
| ===== Module-2 - Interconnects ===== | ===== Module-2 - Interconnects ===== | ||
| Line 97: | Line 100: | ||
| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-2/ee5311-module-2-interconnects.pdf|Lecture Slides]] | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-2/ee5311-module-2-interconnects.pdf|Lecture Slides]] | ||
| + | |||
| + | ===== Module-3 - The Inverter ===== | ||
| + | |||
| + | **Learning Objectives**: | ||
| + | |||
| + | - Explain the functioning of a CMOS inverter | ||
| + | - Explain the Voltage Transfer Characteristics of an inverter | ||
| + | - Derive an expression for the trip point of an inverter | ||
| + | - Derive an expression for the delay of an inverter driving a load | ||
| + | - Derive expressions for Static, Dynamic and Short Circuit power of an inverter. | ||
| + | |||
| + | **Contents**: | ||
| + | - Switch Model | ||
| + | - Transfer Characteristics | ||
| + | - Switching Threshold | ||
| + | - Noise Margin | ||
| + | - Supply Voltage Scaling | ||
| + | - Propagation Delay | ||
| + | - Power | ||
| + | - Dynamic | ||
| + | - Short circuit | ||
| + | - Leakage | ||
| + | |||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-3/ee5311-module-3-inverter.pdf|Lecture Slides]] | ||
| + | |||
| + | ===== Tutorial-2 - The Inverter ===== | ||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/tutorials/ee5311-tut-2.pdf|Tutorial-2]] | ||
| + | |||
| + | ===== Module-4 - Combinational Circuit Design ===== | ||
| + | |||
| + | **Learning Objectives**: | ||
| + | - Explain logical effort (LE) and electrical effort (EE) | ||
| + | - Derive the optimum number of buffers with their sizes to drive a load. | ||
| + | - Implement any arbitrary boolean function in Static CMOS logic | ||
| + | - Derive logical effort for any gate built in any style of logic | ||
| + | - Optimize the path delay of arbitrary gates driving a load capacitance | ||
| + | - Implement logic functions using ratio'd logic and dynamic logic | ||
| + | - Use the pass transistor to implement simple gates like MUX and XORs 8. Explain basic domino logic | ||
| + | |||
| + | **Contents**: | ||
| + | - CMOS gates | ||
| + | - Gate sizing | ||
| + | - Capacitance estimation | ||
| + | - Delay estimation | ||
| + | - Logical effort | ||
| + | - Path delay optimizaion | ||
| + | - Buffer insertion | ||
| + | - Circuit Families | ||
| + | - Static CMOS | ||
| + | - Ratioed gates | ||
| + | - Cascode Voltage Switch Logic (CVSL) & Level Translators | ||
| + | - Dynamic circuits | ||
| + | - Pass Transistor circuits | ||
| + | |||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-4/ee5311-module-4-comb-ckt.pdf|Lecture Slides]] | ||
| + | |||
| + | ===== Tutorial-3 - Combinational Circuits ===== | ||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/tutorials/ee5311-tut-3.pdf|Tutorial-3]] | ||
| + | |||
| + | |||
| + | |||