Comparison table for references below.

Hearing aid processor: Papers and product

• AIC111 data sheet
• J. W. Fattaruso, J. R. Hochschild, W. Sjursen, L. Fang, D. G. Gata, C. M. Branch, J. Holmes, Z. Jiang, S. Chen, K. Ling, E. Petilli, M. L. Skorcz, R. R. Dickerson, and W. A. Severin, “Analog processing circuits for a 1.1V 270µA mixed-signal hearing aid chip,” IEEE International Solid-State Circuits Conference, vol. XLV, pp. 384 - 385, February 2002. paper, slides.
• D. G. Gata, W. Sjursen, J. R. Hochschild, J. W. Fattaruso, L. Fang, G. R. Iannelli, Z. Jiang, C. M. Branch, J. A. Holmes, M. L. Skorcz, E. M. Petilli, S. Chen, G. Wakeman, D. A. Preves, and W. A. Severin, “A 1.1-V 270-µA mixed-signal hearing aid chip,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1670 - 1678, December 2002. paper

Many papers describing hearing aid calibration for the human ear, analog front end, AGC requirements.

• S. Kim, S. J. Lee, N. Cho, S. Song, and H. Yoo, “A fully integrated digital hearing aid chip with human factors considerations,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 266 - 274, January 2008. paper
• S. Kim, S. J. Lee, N. Cho, S. Song, and H. Yoo, “A fully integrated digital hearing-aid chip with human-factors considerations,” IEEE International Solid-State Circuits Conference, vol. XL, pp. 154 - 155, February 2007. paper, slides
• S. Kim, J. Lee, S. Song, N. Cho, and H. Yoo, “An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 876 - 882, April 2006. paper
• S. Kim, J. Lee, S. Song, N. Cho, and H. Yoo, “An energy-efficient analog front-end circuit for a sub-1V digital hearing aid chip,” Symp. VLSI Circuits Dig. , pp. 176 - 179, June 2005. paper

• F. Serra-Graells, L. Gómez, and J. L. Huertas, “A true-1-V 300-µW CMOS-subthreshold log-domain hearing-aid-on-chip,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1271 - 1281, August 2004. paper

Resistive feedback PGA with linear dB steps from -1dB to 40dB. Using e^x=(1+x/2)/(1-x/2), one can get linear in dB steps for linear changes in R₂ and R₁. This fine stepping is used for a 4dB range, and then R₂ and R₁ are reset to new values and the process repeated. This results in resistor strings with equal increments. The feedback resistor has one string, and the input resistor has ten strings, one for each 4dB range from 40dB to 0dB. The PGA operates with ~ 400mV full scale and a gain of 2.1 is built into the 1 bit delta sigma modulator. Bandwidth=10kHz * opamp schematic

An additional input for feed from telecoil is incorporated. The input resistor array is duplicated on one side and multiplexed to the input terminal of the opamp. Some clarifications about the telecoil are here

1bit, OSR=128, CIFB, 1st opamp has assistant, feedforward path for swing reduction.

• 1bit 2.56MHz input, 16 bits 40kHz output (signal bandwidth=10kHz)
• SINC⁴, 32 taps in each
• 10th order halfband
• 36th order FIR
• 1st order IIR Highpass, 50Hz/100Hz/0Hz low frequency cutoff
• 15.2μW, xx mm²
• 0.13μm SP standard cell library

This spreadsheet has a number of sheets summarizing the results of the PGA and the ADC.

The below pdf provides technical details of the design that has been taped out.

Backend of the digital Hearing aid

• This document shows our understanding of what the interface should do. The last page has clarifications from Mr. Biju Oommen.