Class D Audio amplifiers-Self study course, Aug.-Dec. 2008
Co-ordinator: Nagendra Krishnapura
Knowledge of Fourier and Laplace transforms, feedback systems, and
CMOS digital gates.
This is a self study course. Students are expected to understand
the operation of class D amplifiers After this self study, you should
You can learn about all of these by going through the references below.
- know half bridge, full bridge, and bridged three level(filterless) class D driver topologies
- be able to design the driving switches and appropriate driving circuitry for them to maximize efficiency
- be able to simulate complete closed loop class D amplifier with a transistor level driver and ideal models of the remaining blocks
- be able to use FFTs and windowing correctly to analyze the spectral content of signals that are not necessarily periodic
- understand the simulation results!
At the end of the semester, you should show simulations of a half bridge and bridged three level class D drivers in open loop and closed loop. In all simulations, you have to model the source and drain junction parasitics.
You should show the following simulation results for all 4 configurations above.
- The switching frequency is 300kHz.
- Speaker impedance is 8Ω
- The maximum power driven by the half bridge must be at least 40mW.(This is way smaller than what is possible with a 1.8V supply. This should be achievable even if you have a very poor switch.
- The maximum power driven by the bridged three level drivers must be at least 160mW.
- The switches and their drivers must be designed in a 0.18µm CMOS process with a 1.8V supply. The inputs must have minimum sized inverters.
- Arrangements must be made to prevent simultaneous conduction of top and bottom switches. The logic required for this must be designed at the transistor level.
- Macromodels(ideal controlled sources or verilogA) can be used for the remaining blocks.
- Total harmonic distortion(within the audio band-20kHz) at half the maximum power level should be less than 0.5%.
- A second order LC filter should be used with the half bridge. Its attenuation or peaking at the edge of the audio band must be less than 1.5dB.
Information on transistor models and simulators can be found here. The speaker can be modelled as an 8Ω resistor for all simulations. After the design is complete, use the speaker model below and compare the results to those with an 8Ω resistor.
- Distortion versus output power level
- Distortion versus signal frequency at half maximum power level(20mW for the half bridge topology, 80mW for the bridged three level topology)
- Efficiency versus output power level(Efficiency is the ratio of the audio power delivered to the speaker to the power drawn from the power supply by the switches, the buffers driving them, and the circuitry used to generate the drive waveforms, in other words, everything that is designed at the transistor level)
Half bridge class D amplifier
Click here for a pdf figure.
You can similarly derive the bridged three level topology from the references.
- Synopsis: 20%
- Simulation demo: 30%
- Written test: 20% (12th Nov. 2008)
- Viva: 30% (12th Nov. 2008)
All references to IEEE articles are available from
IEEE Explore which can be
accessed through institute proxy 10.65.0.31/32/33.
Class D amplifiers
- Wikipedia article
- Notes on Class D amplifier from Georgia Institute of Technology
- Notes from Elliott Sound Products
- Brett Forejt, Vijay Rentala, Jose Duilio Arteaga, and Gangadhar Burra, "A 700+-mW Class D Design With Direct Battery Hookup in a 90-nm Process," IEEE Journal of Solid-State Circuits, Volume 40, Issue 9, Sep. 2005, pp. 1880-1887.
- Varona et al., "A Low-Voltage Fully-Monolithic ΔΣ-Based Class-D Audio Amplifier," Proceedings of the 1999 European Solid State Circuits Conference, pp. 545-548. (This has an example of switch sizing. This is not the type of class D amplifier you are required to design)
- Putzeys B., "Digital audio's final frontier," IEEE Spectrum vol. 40, no. 3, Mar. 2008. pp. 34-41.
- Berkhout M., "Audio at low and high power," Proceedings of the 2008 European Solid State Circuits Conference pp. 40-49.
- Application notes from companies
Taking FFTs and windowing