Integrated Circuits and Systems group, IIT Madras

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
Next revision Both sides next revision
start [2019/01/26 18:31]
nagendra
start [2020/04/29 09:35]
nagendra
Line 8: Line 8:
  
 <​html><​center><​iframe width="​560"​ height="​315"​ src="​https://​www.youtube.com/​embed/​wAZWBAM6-Ts"​ frameborder="​0"​ allowfullscreen></​iframe></​center></​html>​ <​html><​center><​iframe width="​560"​ height="​315"​ src="​https://​www.youtube.com/​embed/​wAZWBAM6-Ts"​ frameborder="​0"​ allowfullscreen></​iframe></​center></​html>​
 +
 +=====  Reserch programs at IIT Madras =====
 +  * Apply to our PhD and MS programs at research.iitm.ac.in. You can find more information at [[http://​www.ee.iitm.ac.in/​~nagendra/​generalinfo-researchprograms.html|this link]]. ​
  
 ===== News ===== ===== News =====
-  * [[http://​www.ee.iitm.ac.in/​vlsi/​_detail/​iscas2019papers.png?id=start|papers]] from our group will be presented ​at the 2019 International Symposium on Circuits and Systems to be held in Sapporo, Japan, in May 2019. Congratulations to all authors+  ​* The paper **A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and >100 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC** by Alok Baluni and Shanthi Pavan was presented at the IEEE Custom Integrated Circuits Conference in Mar. 2020. This  paper won the **outstanding student paper award** at the conference, and will be presented at the plenary at CICC 2021. Congratulations Alok! 
-  * Vaibhav and Chakravarti have joined our group. A warm welcome to them! + 
-  * The paper **A 25-to-38GHz,​ 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios** by Abhishek Bhat and Nagendra Krishnapura is accepted for presentation at the 2019 International Solid-State Circuits Conference to be held in San Francisco in Feb. 2019+  * The paper **An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter** by Hajime Shibata,​...,​ and Shanthi Pavan was presented at the 2020 IEEE International Solid State Circuits Conference in San Francisco in Feb. 2020. 
 + 
 +  ​* [[http://​www.ee.iitm.ac.in/​vlsi/​_detail/​iscas2020papers.png|11 papers]] from the group have been accepted for presentation ​at the 2020 International Symposium on Circuits and Systems to be held in SevilleSpain in May 2020. Congratulations to all authors. ​
  
  
 ([[newsarchives|Archive]]) ([[newsarchives|Archive]])