D.J. Allstot, S. Aniruddhan, G. Banerjee, M. Chu, X. Li, J. Paramesh, S. Shekhar and K. Soumyanath, “Circuit techniques for CMOS multiple-antenna transceivers,” 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers
, Long Beach, CA, USA, 2005, pp. 225-228. doi: 10.1109/RFIC.2005.1489639
* D.J. Allstot, S. Aniruddhan, M. Chu, J. Paramesh and S. Shekhar,”Recent advances and design trends in CMOS radio frequency integrated Circuits“, International Journal of High Speed Electronics and Systems
, vol.15, no.2, pp 377-428, June 2005. doi: 10.1142/9789812774583_0006
* V.Vasudevan, “Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits,” Proceedings. 42nd Design Automation Conference
, 2005., Anaheim, CA, 2005, pp. 397-402. doi: 10.1145/1065579.1065685
* S. Aniruddhan and D.J. Allstot, “Architectural issues in base-station frequency synthesizers,” 2005 IEEE International Symposium on Circuits and Systems
, Kobe, 2005, pp. 6034-6037 Vol. 6. doi: 10.1109/ISCAS.2005.1466015
* S. Ramachandran and S. Srinivasan, “Design and FPGA Implementation of an MPEG based Video Scalar with reduced on-chip memory utilization”, Journal of Systems Architecture, Elsevier Publications
, Vol. 51, pp. 435-450, 2005. doi: 10.1016/j.sysarc.2004.07.008
* K.N. Vikram, V. Vasudevan and S.Srinivasan, “Rate-distortion estimation for fast JPEG2000 compression at low bit-rates,” Electronics Letters
, vol. 41, no. 1, pp. 16-18, 6 Jan. 2005. doi: 10.1049/el:20057147
* S.Singh and S.Srinivasan, “Architecturally efficient FFT pruning algorithm,” Electronics Letters
, vol. 41, no. 23, pp. 1305-1306, 10 Nov. 2005. doi: 10.1049/el:20052994
* P.Rajesh Kumar, K.Sridharan and S.Srinivasan, “An efficient algorithm for topological map construction in a planar environment explored using proximity sensors,” Proceedings of 2005 International Conference on Intelligent Sensing and Information Processing
, 2005., Chennai, India, 2005, pp. 67-72. doi: 10.1109/ICISIP.2005.1529422
===== 2004 =====
* K.P. Sunil Rafeeque and V.Vasudevan, “A Built-In-Self-Test Scheme for Segmented and Binary Weighted DACs”, Journal of Electronic Testing:Theory and Applications
, vol. 20, pp 623-638, Dec. 2004. doi: 10.1007/s10677-004-4250-4
* K.P.S.Rafeeque and V.Vasudevan, “A built-in-self-test scheme for digital to analog converters,” 17th International Conference on VLSI Design. Proceedings.
, Mumbai, India, 2004, pp. 1027-1032. doi: 10.1109/ICVD.2004.1261065
* K.P.Sunil Rafeeque and V.Vasudevan, “An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC,” 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
, Vancouver, BC, 2004, pp. I-I. doi: 10.1109/ISCAS.2004.1328186
* N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “The hierarchical timing pair model for multirate DSP applications,” IEEE Transactions on Signal Processing
, vol. 52, no. 5, pp. 1209-1217, May 2004. doi: 10.1109/TSP.2004.826178
* S. Aniruddhan, M.Chu and D.J. Allstot, “A lateral-BJT-biased CMOS voltage-controlled oscillator,” 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
, Vancouver, BC, 2004, pp. I-976. doi: 10.1109/ISCAS.2004.1328360
* S. Pavan, “A fixed transconductance bias technique for CMOS analog integrated circuits,” 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
, Vancouver, BC, 2004, pp. I-661. doi: 10.1109/ISCAS.2004.1328281
* S. Pavan, “Continuous-time integrated FIR filters at microwave frequencies,” IEEE Transactions on Circuits and Systems II: Express Briefs
, vol. 51, no. 1, pp. 15-20, Jan. 2004. doi: 10.1109/TCSII.2003.821522
* V.Vasudevan, “A time-domain technique for computation of noise-spectral density in linear and nonlinear time-varying circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 51, no. 2, pp. 422-433, Feb. 2004. doi: 10.1109/TCSI.2003.822553
* V.Vasudevan, “A simple technique to evaluate the noise spectral density in operational amplifier based circuits using the adjoint network theory,” IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 51, no. 11, pp. 2175-2178, Nov. 2004. doi: 10.1109/TCSI.2004.836858
* V.Vasudevan and M.Ramakrishna “Computation of the average and harmonic noise power-spectral density in switched-capacitor circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 51, no. 11, pp. 2165-2174, Nov. 2004. doi: 10.1109/TCSI.2004.836844
* Kavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti and V. Bala Kuteshwar, “A parallel architectural implementation of the New Three-Step Search algorithm for block motion estimation,” 17th International Conference on VLSI Design. Proceedings.
, Mumbai, India, 2004, pp. 1071-1076. doi: 10.1109/ICVD.2004.1261071
* Q. Khan, S. K. Wadhwa and K. Misri, “A tunable g/sub m/-C filter with low variation across process, voltage and temperature,” 17th International Conference on VLSI Design. Proceedings.
, Mumbai, India, 2004, pp. 539-544. doi: 10.1109/ICVD.2004.1260975
===== 2003 =====
* N. Krishnapura and Y. Tsividis, “Micropower low-voltage analog filter in a digital CMOS process,” IEEE Journal of Solid-State Circuits
, vol. 38, no. 6, pp. 1063-1067, June 2003. doi: 10.1109/JSSC.2003.811986
* S. Kudszus, A. Shahani, S.Pavan, D. Schaffer and M. Tarsia, “A 46-GHz distributed transimpedance amplifier using SiGe bipolar technology,” IEEE MTT-S International Microwave Symposium Digest
, 2003, Philadelphia, PA, USA, 2003, pp. 1387-1390 vol.2. doi: 10.1109/MWSYM.2003.1212630
* S. Pavan, ” Analog FIR Filters at Microwave Frequencies,“ Proceedings of the National Conference on Communications
, IIT Madras, Chennai, February 2003. paper
* V.Vasudevan and M.Ramakrishna, “Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique,” Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)
, Anaheim, CA, 2003, pp. 538-541. doi: 10.1145/775832.775968
* V.Vasudevan, “A time-domain technique for computation of noise spectral density in switched capacitor circuits,” Proceedings of the 2003 International Symposium on Circuits and Systems
, 2003. ISCAS '03., Bangkok, 2003, pp. I-I.. doi: 10.1109/ISCAS.2003.1205631
* Y. Tsividis, N. Krishnapura, Y. Palaskas and L. Toth, “Internally varying analog circuits minimize power dissipation,” IEEE Circuits and Devices Magazine
, vol. 19, no. 1, pp. 63-72, Jan. 2003. doi: 10.1109/MCD.2003.1175109
* Srikar Movva and S. Srinivasan, “A novel architecture for lifting-based discrete wavelet transform for JPEG2000 standard suitable for VLSI implementation,” 16th International Conference on VLSI Design
, 2003. Proceedings., New Delhi, India, 2003, pp. 202-207. doi: 10.1109/ICVD.2003.1183137
* K. Gupta and S. Srinivasan, “Reduced memory implementation of modified serial watershed algorithm based on ordered queue,” Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing
, Las Vegas, NV, USA, 2003, pp. 514-518. doi: 10.1109/ITCC.2003.1197582
* A. Kishore and S. Srinivasan, “A distributed memory architecture for morphological image processing,” Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing
, Las Vegas, NV, USA, 2003, pp. 536-540. doi: 10.1109/ITCC.2003.1197586
* S. Ramachandran and S. Srinivasan, “Design and FPGA implementation of a video scalar with on-chip reduced memory utilization,” Euromicro Symposium on Digital System Design
, 2003. Proceedings., Belek-Antalya, Turkey, 2003, pp. 206-213. doi: 10.1109/DSD.2003.1231927
* P.Rajesh Kumar, N. Sudha, S. Srinivasan and K. Sridharan, “A pipelined cellular architecture for Euclidean distance transform,” TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region
, Bangalore, India, 2003, pp. 1153-1156 Vol.3. doi: 10.1109/TENCON.2003.1273428
* Q. Khan and D. Dutta, “A programmable CMOS bandgap voltage reference circuit using current conveyor,” 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003
, Sharjah, 2003, pp. 8-11 Vol.1. doi: 10.1109/ICECS.2003.1301963
* Q. Khan, S. Wadhwa and K. Misri, “Low power startup circuits for voltage and current reference with zero steady state current,” Proceedings of the 2003 International Symposium on Low Power Electronics and Design
, 2003. ISLPED '03., Seoul, South Korea, 2003, pp. 184-188. doi: 10.1109/LPE.2003.1231859
* Q. Khan, S. Wadhwa and K. Misri, “A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature,” 16th International Conference on VLSI Design, 2003. Proceedings.
, New Delhi, India, 2003, pp. 504-506. doi: 10.1109/ICVD.2003.1183184
===== 2002 =====
* N. Chandrachoodan, “Performance Analysis and Hierarchical Timing for DSP System Synthesis”, PhD thesis, Department of Electrical and Computer Engineering
, University of Maryland, College Park, August 2002. Paper
* N. Chandrachoodan, S. S. Bhattacharyya, and K. J. R. Liu. “High-level synthesis of DSP applications using adaptive negative cycle detection.”, EURASIP Journal on Applied Signal Processing
, 2002(9):893-907, September 2002. doi: 10.1155/S1110865702205053
* S.Ramachandran and S.Srinivasan, “A fast FPGA-based MPEG-2 image encoder with a novel automatic quality control scheme” Elsevier Science, Microprocessors and Microsystems
, Vol.25, pp. 449-457, 2002 doi: 10.1016/S0141-9331(01)00138-7
* S. Ramachandran and S. Srinivasan, “A novel automatic quality control scheme for real time image transmission,” VLSI Design Journal
, USA, Vol. 14(4), pp. 329-335, 2002. doi: 10.1080/10655140290011131
* S. Ramachandran and S. Srinivasan, “A dynamically reconfigurable video compression scheme using FPGAs with coarse-grain parallelism”, VLSI Design Journal
, USA Vol. 15(2), pp. 521-528, 2002. doi: 10.1080/1065514021000012138
* K. Seth and S. Srinivasan, “Data scheduling scheme for power reduction in DWT-based image coders,” Electronics Letters
, vol. 38, no. 9, pp. 408-409, 25 April 2002. doi: 10.1049/el:20020291
* Kavish Seth and S.Srinivasan, “VLSI implementation of 2-D DWT/IDWT cores using 9/7-tap filter banks based on the non-expansive symmetric extension scheme,” Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design
, Bangalore, India, 2002, pp. 435-440. doi: 10.1109/ASPDAC.2002.994959
===== 2001 =====
* D. Frey, Y. Tsividis, G. Efthivoulidis and N. Krishnapura, “Syllabic-companding log domain filters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol. 48, no. 4, pp. 329-339, April 2001. doi: 10.1109/82.933791
* G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, “A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation,” Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)
, San Diego, CA, 2001, pp. 153-156. doi: 10.1109/CICC.2001.929745
* N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “Adaptive negative cycle detection in dynamic graphs,” ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
, Sydney, NSW, 2001, pp. 163-166 vol. 5. doi: 10.1109/ISCAS.2001.922010
* N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “An efficient timing model for hardware implementation of multirate dataflow graphs,” 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)
, Salt Lake City, UT, USA, 2001, pp. 1153-1156 vol.2. doi: 10.1109/ICASSP.2001.941126
* N. Chandrachoodan, S. S. Bhattacharyya and K. J. R. Liu, “The hierarchical timing pair model.”, Proceedings of the International Symposium on Circuits and Systems
, pages V-367-V-370, Sydney, Australia, May 2001. doi:10.1109/ISCAS.2001.922061
* N. Krishnapura and Y. Tsividis, “A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process,” 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)
, Kyoto, Japan, 2001, pp. 179-182. doi: 10.1109/VLSIC.2001.934231
* N. Krishnapura and Y. Tsividis, “Dynamically biased 1 MHz low-pass filter with 61 dB peak SNR and 112 dB input range,” 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)
, San Francisco, CA, USA, 2001, pp. 360-361. doi: 10.1109/ISSCC.2001.912673
* N. Krishnapura and Y. Tsividis, “Noise and power reduction in filters through the use of adjustable biasing,” IEEE Journal of Solid-State Circuits
, vol. 36, no. 12, pp. 1912-1920, Dec. 2001. doi: 10.1109/4.972141
* S.Ramachandran and S.Srinivasan, “FPGA Implementation of a Novel, Fast Motion Estimation Algorithm for Real-Time Video Compression,” Ninth International Symposium on Field Programmable Gate Arrays
, Monterey, California, USA, Feb., 2001. doi: 10.1145/360276.360358
===== 2000 =====
* K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process”, IEEE Journal of Solid State Circuits
, December 2000. doi:10.1007/978-1-4757-3198-9_2
* K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A 700M Sample/s 6 b read channel A/D converter with 7 b servo mode,” 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)
, San Francisco, CA, USA, 2000, pp. 426-427. doi: 10.1109/ISSCC.2000.839844
* K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, “A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS”, Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000. doi:10.1007/978-1-4757-3198-9_2
* N. Krishnapura and P. Kinget, “A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS,” IEEE Journal of Solid-State Circuits
, vol. 35, no. 7, pp. 1019-1024, July 2000. doi: 10.1109/4.848211
* N. Krishnapura, Y. Tsividis and D. R. Frey, “Simplified technique for syllabic companding in log-domain filters,” Electronics Letters
, vol. 36, no. 15, pp. 1257-1259, 20 July 2000. doi: 10.1049/el:20000978
* S. Pavan and Y. Tsividis, “Time-scaled electrical networks. Properties and applications in the design of programmable analog filters,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol. 47, no. 2, pp. 161-165, Feb. 2000. doi: 10.1109/82.823547
* S. Pavan, Y. Tsividis and K. Nagaraj, “Widely programmable high-frequency continuous-time filters in digital CMOS technology,” IEEE Journal of Solid-State Circuits
, vol. 35, no. 4, pp. 503-511, April 2000. doi: 10.1109/4.839910
* Shrenik Patel and S.Srinivasan, ““Modified embedded zerotree wavelet algorithm for fast implementation of wavelet image codec,” Electronics Letters
, vol. 36, no. 20, pp. 1713-1714, 28 Sept. 2000. doi: 10.1049/el:20001212
* S.Ramachandran and S.Srinivasan, “A programmable pruning level control based MPEG video encoder,” 2000 IEEE International Symposium on Circuits and Systems (ISCAS)
, Geneva, Switzerland, 2000, pp. 571-574 vol.1. doi: 10.1109/ISCAS.2000.857159
* S.Ramachandran and S.Srinivasan, “Design and implementation of an EPLD-based variable length coder for real time image compression applications,” 2000 IEEE International Symposium on Circuits and Systems (ISCAS)
, Geneva, Switzerland, 2000, pp. 607-610 vol.1. doi: 10.1109/ISCAS.2000.857168
===== 1999 =====
* N. Krishnapura and P. Kinget, “A 5.3GHz programmable divider for HiPerLAN in 0.25 µm CMOS,” Proceedings of the 25th European Solid-State Circuits Conference
, Duisburg, Germany, 1999, pp. 142-145. Paper
* S. Pavan, Y. Tsividis and K. Nagaraj, “A 60-350 MHz programmable analog filter in a digital CMOS process,” Proceedings of the 25th European Solid-State Circuits Conference
, Duisburg, Germany, 1999, pp. 46-49. Paper
* S. Pavan, Y. Tsividis and K. Nagaraj, “Modeling of accumulation MOS capacitors for analog design in digital VLSI processes,” 1999 IEEE International Symposium on Circuits and Systems (ISCAS)
, Orlando, FL, 1999, pp. 202-205 vol.6. doi: 10.1109/ISCAS.1999.780130
* D.V.R. Murthy, S. Ramachandran and S. Srinivasan, “Parallel implementation of 2D-discrete cosine transform using EPLDs,” Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), Goa, India, 1999, pp. 336-339. doi: 10.1109/ICVD.1999.745178
* S.Ramachandran, S.Srinivasan and R.Chen, “EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression,” 1999 IEEE International Symposium on Circuits and Systems (ISCAS)
, Orlando, FL, 1999, pp. 375-378 vol.3. doi: 10.1109/ISCAS.1999.778863
* T.G.Venkatesh and S.Srinivasan, “A pruning based fast rate control algorithm for MPEG coding,” Proceedings Third International Conference on Computational Intelligence and Multimedia Applications. ICCIMA'99 (Cat. No.PR00300)
, New Delhi, India, 1999, pp. 403-407. doi: 10.1109/ICCIMA.1999.798564
===== 1998 =====
* L. Toth, Y. Tsividis, and N. Krishnapura, “Analysis of noise and interference in companding signal processors,” 1998 IEEE International Symposium on Circuits and Systems (ISCAS)
, Monterey, CA, 1998, pp. 143-146 vol.1. doi: 10.1109/ISCAS.1998.704209
* L. Toth, Y. Tsividis, and N. Krishnapura, “On the analysis of noise and interference in instantaneously companding signal processors,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol. 45, no. 9, pp. 1242-1249, Sept. 1998. doi: 10.1109/82.718591
* N. Krishnapura, S. Pavan, C. Mathiazhagan and B. Ramamurthi, “A baseband pulse shaping filter for Gaussian minimum shift keying,” 1998 IEEE International Symposium on Circuits and Systems (ISCAS)
, Monterey, CA, 1998, pp. 249-252 vol.1. doi: 10.1109/ISCAS.1998.704333
* N. Krishnapura, Y. Tsividis, K. Nagaraj and K. Suyama, “Companding switched capacitor filters,” ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
, Monterey, CA, 1998, pp. 480-483 vol.1. doi: 10.1109/ISCAS.1998.704507
* S. Pavan and Y. Tsividis, “An analytical solution for a class of oscillators, and its application to filter tuning,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
, vol. 45, no. 5, pp. 547-556, May 1998. doi: 10.1109/81.668866
* S. Pavan and Y. Tsividis, “An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning”, IEEE Transactions on Circuits and Systems-I
, vol. 45, no. 9, pp. 1242-1249, May 1998. (paper) doi: 10.1109/81.668866
* S. Venkatesh and S. Srinvasan, “Modified butterfly structure for efficient implementation of pruned fast cosine transform,” Electronics Letters
, vol. 34, no. 14, pp. 1383-1385, 9 July 1998. doi: 10.1049/el:19980977
* S. Srinivasan and B. Srikanth, “Implementation Of A Fast Data Access Architecture For Two Dimensional Applications, International Conference on Computational Intelligence and Multimedia Applications
, Churchill, Australia, Feb 1998.
* S. Venkatesh, S. Srinivasan and R.Chen, “An efficient implementation of a progressive image transmission system using successive pruning algorithm on a parallel architecture,” Proceedings. Fifth International Conference on High Performance Computing (Cat. No. 98EX238)
, Madras, India, 1998, pp. 445-451. doi: 10.1109/HIPC.1998.738020
====== Patents ======
* M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, “Current measurments in switching regulators”, US 9,755,518, September 5, 2017. US9755518B2
* M. Bansal, Q. Khan and C. Shi, “Average current mode control of multi-phase switching power converters, US 9,442,140, Sep. 13, 2016. JP6185194B2
* Qadeer A. Khan,Sandeep Chaman Dhar,Joshua A. ZAZZERA,Todd R. Sutton, “Circuits and Methods for Driving Resonant Actuators”, US 9,344,022, May 17, 2016. WO2015038703A1
* Davinder Aggarwal, Vibhor Jain and Janakiraman VIRARAGHAVAN, “Automated design rule checking (DRC) test case generation”, US 8,875,064, Oct 28, 2014. US8875064B2
* Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh and Janakiraman VIRARAGHAVAN, “Generic design rule checking (DRC) test case extraction”, US 9,292,652, Mar 22 2016. US9292652B2
* C. Narathong and S. Aniruddhan, “Multi-mode Configurable Transmitter Circuit”, US 8,099,127, Jan. 17, 2012. US8099127B2
* C. Narathong, S. Aniruddhan and W. Su, “Amplifier with Gain Expansion Stage”, US 8,035,443, Oct. 11, 2011. US8035443B2
* B. Sun, S. Aniruddhan and S. Sridhara, “Method and Apparatus for Divider Unit Synchronization”, US 7,965,111, Jun. 25, 2011. US7965111B2
* S. Aniruddhan, B. Sun, A. Jayaraman and G.S. Sahota, “Mixer with High Output Power Accuracy and Low Local Oscillator Leakage”, US 7,941,115, May 10, 2011. US7941115B2
* C. Narathong and S. Aniruddhan, “Techniques for improving Balun Loaded-Q”, US 7,863,986, Jan. 4, 2011. US20100033253A1
* Q. Khan, S. Wadhwa, D. Tripathi, G.K. Sidhartha and K. Misri, “PVT Variation Detection and Compensation Circuit”, US 7495465, Feb. 24, 2009. US7495465B2
* D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri and S. Wadhwa, “PVT Variation Detection and Compensation Circuit”, US 7446592, Nov. 4, 2008. US7446592B2
* Q. Khan and G.K. Sidhartha, “Sequence-independent Power-on Reset for Multi-Voltage Circuits”, US 7432748, Oct. 7, 2008. US7432748B2
* D. Tripathi and J. Banerjee, Q. Khan, “Differential Receiver Circuit”, US 7414462, Aug. 19, 2008. US7414462B2
* Q. Khan, H. Fukazawa and T. Nandurkar, “Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit”, US 7388422, Jun. 17, 2008. US7388422B2
* G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa and K. Misri, “PVT Variation Detection and Compensation Circuit”, US 7388419, Jun. 17, 2008. US7388419B2
* Isaac Shpantzer,Michael Tseytlin,Yaakov Achiam,Aviv Salamon,Israel Smilanski,Olga Ritterbush,Pak Shing Cho,Li Guoliang,Jacob Khurgin,Yehouda Meiman,Alper Demir,Peter Feldman,Peter Kinget,Nagendra Krishnapura,Jaijeet Roychowdhury,Joseph Schwarzwalder and Charles Sciabarra, “System and method for code division multiplexed optical communication”, US 7,167,651, Jan. 23, 2007. US7167651B2
* Q. Khan and D. Tripathi, “Transmission Line Driver Circuit”, US 7292073, Nov. 6, 2007. US7292073B2
* D. Tripathi, Q. Khan and K. Misri, “Transmission Line Driver”, US 7187197, Mar. 6, 2007. US7187197B2
* S. Wadhwa, Q. Khan, K. Misri and D. Muhury, “Digital Clock Frequency Doubler”, US 7132863, Nov. 7, 2006. US7132863B2
* Q. Khan, D. Tripathi and K. Misri, “High Voltage Level Converter Using Low Voltage Devices”, US 7102410, Sep. 5, 2006. US7102410B2
* Q. Khan, S. Wadhwa and K. Misri, Bandgap Reference Circuit, US 7084698, Aug. 1, 2006. US7084698B2
* Q. Khan, S. Wadhwa and K. Misri, “Bidirectional Level Shifter”, US 7061299, Jun, 13, 2006. US7061299B2
* Q. Khan, S. Wadhwa and K. Misri, “Single Supply Level Shifter”, US 7009424, Mar. 7, 2006. US7009424B2
* Shanthi Pavan, “Integrated circuit implementation for power and area efficient adaptive equalization”, US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California. US7142596B2
* Isaac Shpantzer, Yehouda Meiman, Michael Tseytlin, Olga Ritterbush, Aviv Salamon, Peter Feldman,Alper Demir,Peter Kinget, Nagendra Krishnapura and Jaijeet Roychowdhury, “System and method for orthogonal frequency division multiplexed optical communication”, US 7,076,169, Jul. 11, 2006. US7076169B2
* John S. Wang, Sudeep Bhoja, Shanthi Pavan and Hai Tao, “Method and apparatus for improved high-speed adaptive equalization”, US 7,003,228, Feb. 21, 2006. US7003228B2
* George Palaskas and Shanthi Y. Pavan, “Mobility Compensation in MOS Integrated Circuits”, US 6,822,505, 23 Nov. 2004. US6822505B1
* N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,816,003, Nov. 9, 2004. US6816003B2
* N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,717,461, Apr. 6, 2004. US6717461B2
* N. Krishnapura and Y. Tsividis, “Circuits with Dynamic Biasing”, US 6,683,492, Jan. 27, 2004. US6683492B2
* P. Kinget and N. Krishnapura, “Glitch Free Phase Switching Synthesizer”, US 6,671,341, Dec. 30, 2003. US6671341B1
* Shanthi Pavan and Arvin Shahani, “Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier”, US 6,552,615, 22 Apr. 2003. US6552615B1
* Shanthi Pavan, Sudeep Bhoja and John S. Wang, “Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells”, US 6,545,567, 8 Apr. 2003. US6545567B1
* Shanthi Pavan, “Fixed Transconductance Bias Apparatus”, US 6,400,185, 4 Jun. 2002. US6400185B2
* Krishnaswamy Nagaraj and Shanthi Y. Pavan, “Fast Acting Polarity Detector”, US 6,369,726, 2 Apr. 2002. US6369726B1
* Shanthi Pavan, “Low Distortion Sample-and-Hold Circuit”, US 6,323,697, 27 Nov. 2001. US6323697B1
* Shanthi Pavan, “High Frequency Boost Technique”, US 6,304,134, 16 Oct. 2001. US6304134B1
* P. Kinget and N. Krishnapura, “Programmable Frequency Divider”, US 6,281,721, Aug. 28, 2001. US6281721B1
* Yendluri Shanthi-Pavan, Krishnaswamy Nagaraj and Venugopal Gopinathan, “Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation”, US 5,945,889, 31 Aug. 1999. US5945889A