Integrated Circuits and Systems group, IIT Madras

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
Next revision Both sides next revision
publications:start [2019/03/17 14:31]
qkhan
publications:start [2019/04/22 15:44]
shanthi [2019]
Line 2: Line 2:
  
 ===== 2019 ===== ===== 2019 =====
 +  * Kishalay Dutta, Vinod Menezes and Shanthi Pavan, "​Analysis and design of cyclic switched-capacitor DC-DC converters,"​ // IEEE Transactions on Circuits and Systems: Regular Papers //, (to appear).
 +  * Saravana Manivannan and Shanthi Pavan, "​Degradation of alias rejection in continuous-time bandpass delta-sigma converters due to weak loop filter nonlinearities,"​ //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. ​
 +  * Shanthi Pavan, "​Simplified analysis of total integrated noise in passive switched-capacitor and N-path filters,"​ //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. ​
 +  * Shanthi Pavan, "An alternative approach to Bode's Noise Theorem,"​ //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. ​
   *  Abirmoya Santra, Angelo De Carmine, Guttha Venkata Sesha Rao, Qadeer A. Khan, "A Highly Scalable, Time-Based Capless Low-Dropout Regulator Using Master-Slave Domino Control,"​ //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. (Accepted for presentation).   *  Abirmoya Santra, Angelo De Carmine, Guttha Venkata Sesha Rao, Qadeer A. Khan, "A Highly Scalable, Time-Based Capless Low-Dropout Regulator Using Master-Slave Domino Control,"​ //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. (Accepted for presentation).
   * Chithra and Nagendra Krishnapura,​ "​Static Phase Offset Reduction Technique for Delay Locked Loops,"​ //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. (Accepted for presentation).   * Chithra and Nagendra Krishnapura,​ "​Static Phase Offset Reduction Technique for Delay Locked Loops,"​ //2019 International Symposium on Circuits and Systems (ISCAS)//, 26-29 May 2019, Sapporo, Japan. (Accepted for presentation).
Line 25: Line 29:
   * Arpan Sureshbhai Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan, "A 27.2GHz Bipolar LC-VCO Using Class-C Biasing to Maximize Achievable Fosc in 130nm BiCMOS,"//​ Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//​Florence.   * Arpan Sureshbhai Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan, "A 27.2GHz Bipolar LC-VCO Using Class-C Biasing to Maximize Achievable Fosc in 130nm BiCMOS,"//​ Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//​Florence.
   * Abhishek Kumar, Radha Krishna Ganti, Sankaran Aniruddhan, "A Same-Channel Full-Duplex Receiver Using Direct RF Sampling,"//​ Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//​Florence.   * Abhishek Kumar, Radha Krishna Ganti, Sankaran Aniruddhan, "A Same-Channel Full-Duplex Receiver Using Direct RF Sampling,"//​ Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//​Florence.
-  * Qadeer A. Khan, Saurabh Saxena, Abirmoya Santra, "Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier," ​"// Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//​Florence.+  * Qadeer A. Khan, Saurabh Saxena, Abirmoya Santra, "Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier, "// Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2018,//​Florence.
   * S.Pavan,"​FIR Feedback in Continuous-time Delta Sigma Converters,"//​ Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,//San Diego.   * S.Pavan,"​FIR Feedback in Continuous-time Delta Sigma Converters,"//​ Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,//San Diego.
   * S.Manivannan and S.Pavan,"​A 1 MHz Bandwidth, Filtering Continuous-Time Delta-Sigma ADC with 36 dBFS Out-of-Band IIP3 and 76 dB SNDR,"//​ Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,//San Diego.   * S.Manivannan and S.Pavan,"​A 1 MHz Bandwidth, Filtering Continuous-Time Delta-Sigma ADC with 36 dBFS Out-of-Band IIP3 and 76 dB SNDR,"//​ Proceedings of the IEEE Custom Integrated Circuits Conference (CICC) 2018,//San Diego.
Line 35: Line 39:
   * A.Jain and S. Pavan, "​Continuous-time delta-sigma modulators with time-interleaved FIR feedback,"//​IEEE Transactions on Circuits and Systems: Regular Papers//, ​ Feb. 2018.   * A.Jain and S. Pavan, "​Continuous-time delta-sigma modulators with time-interleaved FIR feedback,"//​IEEE Transactions on Circuits and Systems: Regular Papers//, ​ Feb. 2018.
   * Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan,​ Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer "80Kb Logic Embedded High-K Charge Trap Transistor based Multi-Time-Programmable Memory with no Added Process Complexity"​ IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 949-960, March 2018.    * Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan,​ Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer "80Kb Logic Embedded High-K Charge Trap Transistor based Multi-Time-Programmable Memory with no Added Process Complexity"​ IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 949-960, March 2018. 
 +  * Qadeer. A. Khan, S. Kim and Pavan. K. Hanumolu, "​Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters — An Alternative to Conventional Analog and Digital Controllers,"​ //31st International Conference on VLSI Design (VLSID)//, Pune, Jan. 2018.
  
 ===== 2017 ===== ===== 2017 =====
Line 378: Line 383:
 ====== Patents ====== ====== Patents ======
  
 +  * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker, T. Sutton, Current measurments in switching regulators, US 9,755,518, September 5, 2017.
   * M. Bansal, Q. Khan, C. Shi, Average current mode control of multi-phase switching power converters, US 9,442,140, Sep. 13, 2016.   * M. Bansal, Q. Khan, C. Shi, Average current mode control of multi-phase switching power converters, US 9,442,140, Sep. 13, 2016.
   * Q. Khan, S. Dhar, J. Zazzera, T. Sutton, Circuits and Methods for Driving Resonant Actuators, US 9,344,022, May 17, 2016.   * Q. Khan, S. Dhar, J. Zazzera, T. Sutton, Circuits and Methods for Driving Resonant Actuators, US 9,344,022, May 17, 2016.