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| ====== Publications ====== | ====== Publications ====== | ||
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| + | ===== 2021 ===== | ||
| + | *A.Baluni and S.Pavan,"Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback,"//IEEE Journal of Solid-State Circuits//, vol. 56, no. 4, Nov. 2020. | ||
| ===== 2020 ===== | ===== 2020 ===== | ||
| + | * S.Billa,S.Dixit and S.Pavan,"Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 11, Nov. 2020. | ||
| + | * I. Mondal and N. Krishnapura, "Effects of AC Response Imperfections in True-Time-Delay Lines," //IEEE Transactions on Circuits and Systems II: Express Briefs//, [[https://ieeexplore.ieee.org/document/9209153|doi: 10.1109/TCSII.2020.3027529]]. | ||
| + | * R.Theertham, P.Kootala, S.Billa and S.Pavan, "Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 9, Sept. 2020. | ||
| + | * S.Manivannan and S.Pavan,"Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering," /IEEE Transactions on Circuits and Systems I: Regular Papers//, October 2020. | ||
| + | * R. S. A. Kumar and N. Krishnapura, "Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset," //IEEE Transactions on Circuits and Systems I: Regular Papers//, [[https://ieeexplore.ieee.org/document/9169793|doi: 10.1109/TCSI.2020.3013691]]. | ||
| + | * Chithra and N. Krishnapura, "A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems," //IEEE Transactions on Circuits and Systems I: Regular Papers//, vol. 67, no. 6, pp. 1892-1901, June 2020, [[https://ieeexplore.ieee.org/document/8984721|doi: 10.1109/TCSI.2020.2969977]]. | ||
| * G. R., J. D. Bandarupalli, S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | * G. R., J. D. Bandarupalli, S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | ||
| * S. Mukherjee, A. Das, S. Seth, S. Saxena, "An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | * S. Mukherjee, A. Das, S. Seth, S. Saxena, "An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | ||
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| * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura, "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | * Vipul Bajaj, Anand Kannan, Minkle Paul, Nagendra Krishnapura, "Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for presentation). | ||
| * A. D. Carmine, A. Santra, Q. Khan, "A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | * A. D. Carmine, A. Santra, Q. Khan, "A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | ||
| - | * K. Peetala, A. Ranjan, R.Ankamreddi, Q. Khan, "An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | + | * K. Peetala, A. Ranjan, R. Aenkamreddi, Q. Khan, "An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). |
| * M. V. Praveen and N. Krishnapura, "High Linearity Transmit Power Mixers Using Baseband Current Feedback," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://ieeexplore.ieee.org/document/8889460|doi: 10.1109/JSSC.2019.2945962]] | * M. V. Praveen and N. Krishnapura, "High Linearity Transmit Power Mixers Using Baseband Current Feedback," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://ieeexplore.ieee.org/document/8889460|doi: 10.1109/JSSC.2019.2945962]] | ||
| + | * A.Baluni and S.Pavan, "A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and >100 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC," // IEEE Custom Integrated Circuits Conference (CICC)//, March 2020. **(Outstanding Student Paper Award)** | ||
| + | * H.Shibata,G.Taylor,..,and S.Pavan, "An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter," //IEEE International Solid State Circuits Conference (ISSCC)//, February 2020. | ||
| ===== 2019 ===== | ===== 2019 ===== | ||