This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision | Next revision Both sides next revision | ||
|
courses:ee6361_2019:start [2019/03/29 07:19] janakiraman |
courses:ee6361_2019:start [2019/04/05 06:23] janakiraman |
||
|---|---|---|---|
| Line 130: | Line 130: | ||
| - M. Kang, S. K. Gonugondla, A. Patil and N. R. Shanbhag, "A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array," in IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 642-655, Feb. 2018. doi: 10.1109/JSSC.2017.2782087 | - M. Kang, S. K. Gonugondla, A. Patil and N. R. Shanbhag, "A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array," in IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 642-655, Feb. 2018. doi: 10.1109/JSSC.2017.2782087 | ||
| - | ===== Class 10 (22 Mar 2018) ===== | + | ===== Class 11 (22 Mar 2018) ===== |
| * Read time calculation | * Read time calculation | ||
| * SOI Technology - Floating body effects on eDRAM | * SOI Technology - Floating body effects on eDRAM | ||
| * Gated Feedback Sense Amplifier | * Gated Feedback Sense Amplifier | ||
| + | |||
| + | G. Fredeman et al., "A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access," in IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 230-239, Jan. 2016. | ||
| + | doi: 10.1109/JSSC.2015.2456873 [[https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7210238|PDF]] | ||
| [[https://forms.gle/8de7B43mobrrEb7A9|In class quiz]] | [[https://forms.gle/8de7B43mobrrEb7A9|In class quiz]] | ||