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--- courses:ee6361_2019:start [2019/03/16 06:20]
janakiraman
+++ courses:ee6361_2019:start [2019/03/23 06:32]
janakiraman
@@ Line 110: / Line 110: @@
 [[https://goo.gl/forms/FG3QAKgnXLlHb4bB3|In class Quiz]]
 [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE6361/Jan-2018/material/EE6361-eDRAM-Janakiraman-2018.pdf|eDRAM Lecture Slides (2018)]]
+===== Class 10 (22 Mar 2018) =====
+  * Write time calculation
+  * Hierarchical sensing
+  * 3T Micro Sense Amp
+  * Micro Sense Amp Evolution
+Barth, J. et al., “A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008. [[http://ieeexplore.ieee.org/document/4443182/|PDF]]
+[[https://forms.gle/7fZHaL8i231yZ9VW7|In class quiz]]
+===== Course Project =====
+**SRAM based In Memory Compute circuit design to implement the Multiply Accumulate Operation**
+==== Reference papers ====
+  - A. Biswas and A. P. Chandrakasan, "CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks," in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 217-230, Jan. 2019. doi: 10.1109/JSSC.2018.2880918
+  - M. Kang, S. K. Gonugondla, A. Patil and N. R. Shanbhag, "A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array," in IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 642-655, Feb. 2018. doi: 10.1109/JSSC.2017.2782087

Integrated Circuits and Systems group, IIT Madras