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courses:ee5311_2019 [2019/10/14 11:38] janakiraman |
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| [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/tutorials/ee5311-tut-3.pdf|Tutorial-3]] | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/tutorials/ee5311-tut-3.pdf|Tutorial-3]] | ||
| + | ===== Module-5 - Sequential Circuits ===== | ||
| + | - Build elementary sequential circuits like latches and flip flops - Static and Dynamic | ||
| + | - Identify devices that affect set up and hold time | ||
| + | - Derive max and min delay constraints for latch/ flip flop based pipeline systems | ||
| + | - Account for clock skew in a pipelined system | ||
| + | - Analyze time borrowing across half cycles and across cycles | ||
| + | - Calculate the maximum clock frequency of operation of a pipelined system | ||
| + | |||
| + | **Contents**: | ||
| + | - Sequencing Elements | ||
| + | - Sequencing Methods | ||
| + | - Flip flop | ||
| + | - Latch | ||
| + | - Delay definitions | ||
| + | - Circuit Implementations of Latch/ Flop | ||
| + | - Static | ||
| + | - Dynamic | ||
| + | - Max delay constraints | ||
| + | - Min delay constraints | ||
| + | - Time Borrowing | ||
| + | |||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-5/ee5311-module-5-seq-ckt.pdf|Lecture Slides]] | ||
| + | |||
| + | ===== Tutorial-4 - Sequential Circuits ===== | ||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/tutorials/ee5311-tut-4.pdf|Tutorial-4]] | ||
| + | |||
| + | | ||
| + | | ||
| + | ===== Module-6 - Adders and Multipliers ===== | ||
| + | **Learning Objectives**: | ||
| + | - Design a full adder with least PMOS stack size using self duality principle | ||
| + | - Construct adder architectures to reduce delay from O(N) to O(\sqrt{N}) - O(log(N)) | ||
| + | - Draw timing diagrams to show the signal propagation of various adders | ||
| + | - Design an array multiplier for both signed and unsigned multiplication | ||
| + | - Optimize the arrary multiplier using the inverting property of a Full Adder | ||
| + | - Derive the Modified Booth Encoding to reduce the number of partial products | ||
| + | - Design and implement a multipler based on the Modified Booth Encoding algorithm | ||
| + | |||
| + | **Contents**: | ||
| + | - Adders | ||
| + | - Basic terminology | ||
| + | - Full adder circuit design | ||
| + | - Inverting Adder | ||
| + | - Carry Save Adder | ||
| + | - Carry Select Adder | ||
| + | - Carry Look Ahead Adder | ||
| + | - Multipliers | ||
| + | - Basic Terminology | ||
| + | - Booth and Modified Booth Encoding | ||
| + | - 2s Complement Arithmetic | ||
| + | - Array Multiplier | ||
| + | - Carry Save Multipler | ||
| + | - Signed multiplication and carry save implementation | ||
| + | - Final Addition | ||
| + | [[http://www.ee.iitm.ac.in/~janakiraman/courses/EE5311/lecture_notes/module-6/ee5311-module-6-adder-mult.pdf|Lecture Slides]] | ||