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+ | ====== Voltage regulator ====== | ||

+ | * **Goals:** | ||

+ | * Design a voltage regulator for positive voltages | ||

+ | * Understand efficiency and regulation of a regulator | ||

+ | * Appreciate some fine points of small signal "ground" | ||

+ | * Understand how to compensate errors due to opamp input bias currents | ||

+ | * Specifications: | ||

+ | * V<sub>in</sub>=9V, V<sub>out</sub>=6V unless mentioned otherwise | ||

+ | * 1.2V reference voltage(from a dc source) | ||

+ | |||

+ | {{vplusreg1.png?400}} | ||

+ | |||

+ | * A voltage regulator is simply a feedback driven voltage controlled voltage source shown above. The input is a temperature stable dc reference(from a bandgap reference, a Zener diode, or a string of forward biased diodes). The feedback resistor can be made variable to have a variable supply such as the one on your bench. In your implementation, realize output voltages of 3V and 6V by shorting out a part of R<sub>1</sub> as shown above. | ||

+ | |||

+ | * The amplifier used in the voltage regulator need not be a general purpose opamp. It needs to meet the following criteria: | ||

+ | * The efficiency of a regulator is V<sub>out</sub>I<sub>out</sub>/V<sub>in</sub>I<sub>in</sub>. V<sub>out</sub> and V<sub>in</sub> are given by the specifications. To maximize efficiency, I<sub>out</sub> should be close to I<sub>in</sub>. i.e. the bias currents in the circuit must be minimized. | ||

+ | * To minimize V<sub>in</sub> required to obtain a given V<sub>out</sub>, the opamp should have the upper swing limit close to the supply rail. This is achieved by having a single transistor in the common emitter(or common source) configuration-i.e. a single saturation voltage drop-between V<sub>in</sub> and V<sub>out</sub>. Such a regulator is known as a low dropout regulator, LDO for short(dropout = V<sub>in</sub>-V<sub>out</sub>). | ||

+ | |||

+ | * In your case, the "opamp" will be realized using bipolar transistors. Therefore, transistors in the input differential pair draw a bias current I<sub>B</sub>. Determine the output voltage in presence of bias currents. How would you overcome this error? | ||

+ | |||

+ | {{vplusreg2.png?200}} | ||

+ | |||

+ | * The above figure shows a scheme for reducing error due to bias currents. What value will you set R<sub>bias</sub> to? | ||

+ | |||

+ | {{vplusreg3.png?400}} | ||

+ | |||

+ | * The above figure shows the complete schematic of the opamp. C<sub>c</sub> is a compensation capacitor. In the small signal picture, C<sub>c</sub> should be conencted between the base of Q<sub>3</sub> and ground. Where should it be connected in the large signal picture? (Hint: think about what happens to the output voltage if there is a jump in the power supply voltage). | ||

+ | |||

+ | * Design the circuit to meet the following requirements. For operating point calculations, you can assume β=∞. | ||

+ | * In no load condition(R<sub>L</sub>=∞), quiescent currents through Q<sub>1,2,3</sub> and the feedback branch R<sub>1</sub>,R<sub>2</sub> are equal | ||

+ | * Quiescent V<sub>CE3</sub> should be 2 to 3V. | ||

+ | * Efficiency when R<sub>L</sub>=125Ω and V<sub>out</sub>=6V is 0.96*V<sub>out</sub>/V<sub>in</sub>. | ||

+ | * C<sub>c</sub> should be adjusted as described below. | ||

+ | |||

+ | * Optimizing the dc operating point: Calculate the resistor values to meet the specifications above. If you try to realize these exact values with series parallel combinations of resistors, the assembly can get quite messy. Therefore: | ||

+ | * Use the nearest standard values available. At most, go for a combination of two resistors for each. | ||

+ | * For the feedback network, use five identical resistors, with four in parallel or series as appropriate to realize the ratio accurately | ||

+ | * Ensure that the collector resistances of Q<sub>1,2</sub> are identical. | ||

+ | * Build the circuit, compensate it if necessary and measure the dc voltages V<sub>c1,c2</sub> at the collectors of Q<sub>1,2</sub>. | ||

+ | * If V<sub>c1</sub> is different from V<sub>c2</sub>, the differential pair is not perfectly balanced. Q<sub>1</sub>'s collector voltage is fixed by the dc operating point of the following stages. Q<sub>2</sub>'s current needs to be reduced by (V<sub>c1</sub>-V<sub>c2</sub>)/R<sub>c</sub>. | ||

+ | * To do this, measure the voltage V<sub>E</sub> at the emitter coupled node and adjust R<sub>E</sub> such that V<sub>E</sub>/R<sub>E,new</sub> = V<sub>E</sub>/R<sub>E</sub>-(V<sub>c1</sub>-V<sub>c2</sub>)/R<sub>c</sub>. | ||

+ | * Again, use the nearest standard value if possible. Ignore mismatch between V<sub>c1</sub> and V<sub>c2</sub> if it is 100mV or less. | ||

+ | |||

+ | * Wire up the amplifier and apply a small signal square wave riding around 1.2V at the reference input and R<sub>L</sub>=∞. Does the amplifier settle without ringing? If not, compensate the loop using a capacitor C<sub>c</sub> as shown in the figure-connect it to the appropriate small signal ground determined above. Start from small values of C<sub>c</sub> and adjust the value to get 5% overshoot. Change R<sub>L</sub> to 125Ω. Does the ringing get better or worse? Why? | ||

+ | |||

+ | * Test the regulator with load(dc test): | ||

+ | * Determine the output voltages for R<sub>L</sub>=∞, 2kΩ, 500Ω, 125Ω. The variation in output voltage with the input voltage is known as line regulation. | ||

+ | * Determine the output voltages for V<sub>in</sub>=8V, 9V, 10V. Determine the line regulation ΔV<sub>out</sub>/ΔV<sub>in</sub> for R<sub>L</sub>=500Ω. | ||

+ | * Determine the minimum V<sub>in</sub> required to get V<sub>out</sub>=6V under full load(125Ω). | ||

+ | * What happens if there is a load capacitor C<sub>L</sub> across R<sub>L</sub>? Is there a value of C<sub>L</sub> beyond which the circuit oscillates? | ||

+ | |||

+ | {{vplusreg4.png?400}} | ||

+ | |||

+ | * An alternative method for frequency compensation of the regulator is shown above. What is the required value of the compensation capacitor C<sub>c</sub>? Determine the value as before. At which load condition will you do this(R<sub>L</sub>=∞ or R<sub>L</sub>=125Ω) to cover all load conditions? {{LM2940.pdf|LM2940}} is compensated in this manner. | ||

+ | |||

+ | * Demonstrate the circuit with a 3V output. | ||

+ | |||

+ | * What is the reason for the relatively poor load regulation? Can you increase the loop gain to improve this? (Hint: bootstrapping may be used to increase the apparent load resistance of the differential amplifier stage). | ||

+ | |||

+ | * **Applications:** Linear voltage regulators, such as the ones on your bench are made of circuits like this one. They also include the voltage reference generator. The "pass transistor" Q<sub>4</sub> is of sufficient rating for the maximum output current(You may be able to see large pass transistors mounted on heatsinks on the backside of some of the power supplies in the lab). Multiple buffer stages may be required(such as Q<sub>3</sub>) to drive the base current of Q<sub>4</sub>. Usually the feedback loops have more stages for more gain. For tracking dual power supplies, there is effectively another feedback circuit that looks like an inverting amplifier with the positive V<sub>out</sub> as the input. On modern integrated circuits housing entire systems, like large portions of a radio, it is common to find even upto a dozen LDOs powering various blocks. {{LM2940.pdf|LM2940}} is an example of a commercially available LDO. Page 12 of the datasheet has the schematic diagram. | ||

+ | |||

+ | ===== Additional information ===== | ||

+ | The choice of a 1.2V reference is not arbitrary. A temperature stable voltage reference can be realized using bipolar transistors. Its output equals 1.2V(= bandgap of silicon extrapolated to absolute zero). For more information about this, see | ||

+ | * Chapter 11, "Design of CMOS Analog Integrated Circuits", Behzad Razavi. | ||

+ | * Problem 4 in [[http://www.ee.iitm.ac.in/~nagendra/EE539/200801/assignments/hw08.pdf|this assignment]] of EE539. | ||