Delta Sigma modulation is a popular technique for realization of low and medium frequency data converters in submicron process technologies with reduced supply voltages. It is well suited for audio and intermediate frequency applications. Continuous-time loop filters offer several advantages over traditional discrete-time counterparts such as inherent antialiasing, realizability at much higher frequencies, and lower power consumption. We are investigating theoretical and practical aspects of continuous-time Delta Sigma modulators in order to develop robust low power realizations.
P. Shettigar and S.Pavan, “Design Techniques for Wideband Continuous-time Delta-Sigma Modulators with FIR Feedback DACs,” IEEE Journal of Solid State Circuits , December 2012.
T. Nandi, K. Boominathan and S.Pavan, “ A Continuous-time Delta Sigma Modulator with 87dB Dynamic Range in a 2MHz Signal Bandwidth Using a Switched-Capacitor Return-to-Zero DAC,” Proceedings of the 2012 Custom Integrated Circuits Conference (CICC) , San Jose, California, 2012.
R.S.Rajan and S.Pavan, “Device Noise in continuous-time delta-sigma modulators,” IEEE Transactions on Circuits and Systems: Regular Papers , September 2012.
V. Singh, N. Krishnapura, S.Pavan, B.Vigraham, D.Behera and N.Nigania “A 16
MHz BW 75 dB DR CT Delta Sigma ADC Compensated for More Than One Cycle Excess Loop Delay,”
IEEE Journal of Solid State Circuits ,August 2012.
A.Jain, N. Muthusubramaniam and S.Pavan, “Analysis and Design of a High Speed Continuous Time Delta Sigma Modulator Using the Assisted Opamp Technique,” IEEE Journal of Solid State Circuits , July 2012.
R.S.Rajan and S.Pavan, “Noise in CT DS Modulators with Switched Capacitor Feedback DACs,” Proceedings of the 2012 IEEE International Symposium on Circuits and Systems (ISCAS) , Seoul, Korea, 2012.
P. Shettigar and S.Pavan, “A 15mW 3.6GS/s CT-Delta Sigma ADC with 36MHz Bandwidth and 83dB Dynamic Range in 90nm CMOS,” Proceedings of the 2012 IEEE International Solid State Circuits Conference (ISSCC) , San Francisco, February 2012. (Winner of the ISSCC 2012 Silk Road Award)
Vikas Singh, Nagendra Krishnapura, Shanthi Pavan, Baradwaj Vigraham, Nimit Nigania, Debasish Behera, “A 16MHz BW 75dB DR CT Delta Sigma ADC compensated for more than one cycle excess loop delay,” Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, San Jose, September 2011.
A. Jain, M. Venkatesan and S. Pavan, “A 4mW 1GS/S Continuous-Time DeltaSigma Modulator with 15.6MHz Bandwidth and 67dB Dynamic Range” Proceedings of the European Solid State Circuits Conference, Helsinki, September 2011.
S. Pavan, “On Continuous-time Delta-Sigma Modulators with Return-to-Open DACs”,
IEEE Transactions on Circuits and Systems : Express Briefs, May 2011.(paper) S. Pavan, “The Inconvenient Truth about Alias Rejection in Continuous-time Delta-Sigma Modulators”, Proceedings of the IEEE International Symposium on Circuits and Systems, May 2011.
S. Pavan, “Alias Rejection of Continuous-time Delta-Sigma Converters with Switched-Capacitor Feedback DACs”,
IEEE Transactions on Circuits and Systems : Regular Papers, February 2011.
(paper) S. Pavan, “High-Performance Continuous-time Delta Sigma Converters,” Educational Sessions of the Custom Integrated Circuits Conference, San Jose, USA, 2010.
S. Pavan, ``Design Techniques for High-Performance Continuous-time Delta Sigma Conversion,“ half day tutorial at the European Solid State Circuits Conference, Seville, Spain, 2010.
V. Singh, N. Krishnapura, S. Pavan, “Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time ΔΣ Modulators,”
IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 9, pp. 676-680, Sep. 2010. (
paper)
S. Pavan, “Efficient simulation of weak nonlinearities in continuous-time oversampling converters”,
IEEE Transactions on Circuits and Systems : Regular Papers, August 2010.
(paper) S. Pavan and P. Sankar, “Power reduction in continuous-time Delta-Sigma Modulators using the assisted opamp technique”,
IEEE Journal of Solid State Circuits, July 2010.
(paper) (most read paper in the IEEE Journal of Solid State Circuits in July 2010, and 11th most downloaded paper from ALL of IEEEXplore in July 2010)link N. Krishnapura, “Efficient Determination of Feedback Dac Errors for Digital Correction in Delta-Sigma A/D Converters,”
2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (
paper,
slides)
S. Parameswaran and N. Krishnapura, “A 100µW Decimator for a 16 Bit 24kHz Bandwidth Audio ΔΣ Modulator,”
2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, 31 May-2 Jun. 2010. (
paper,
slides)
S. Pavan, “Understanding weak nonlinearities in continuous-time oversampling converters”, IEEE International Symposium on Circuits and Systems (ISCAS), Paris, May 2010.
K. Reddy and S.Pavan, “A power efficient continuous time ΔΣ modulator with 15
MHz bandwidth and 70 dB dynamic range”,
Analog Integrated Circuits and Signal Processing, June 2010.
(paper) S. Pavan, “Systematic design centering of continuous-time oversampling converters”,
IEEE Transactions on Circuits and Systems : Express Briefs, March 2010
(paper) S.Pavan and P.Sankar, “A 110-microwatt Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB Dynamic Range”,
European Solid State Circuits Conference (ESSCIRC), Athens, Greece, September 2009 (
paper).
S.Pavan, “Excess Loop Delay Compensation in Continuous-time Delta Sigma Modulators”, IEEE Transactions on Circuits and Systems II : Express Briefs (to appear).
K. Reddy and S.Pavan, “A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15
MHz Bandwidth and 70dB Dynamic Range”,
Proceedings of the European Solid State Circuits Conference, Edinburgh, September 2008.
S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, “A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications,”
IEEE Journal of Solid State Circuits, February 2008.
(paper) S. Pavan and N. Krishnapura, “Oversampling Analog-to-Digital Converters”, Full Day Tutorial at the International Conference on VLSI Design, January 4-8, Hyderabad, India.
P. Sankar and S. Pavan, “Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators”,
IEEE Transactions on Circuits and Systems : Express Briefs, December 2007.
(paper) K. Reddy and S. Pavan, “Fundamental Limitations of Continuous-time Delta Sigma Modulators due to Clock Jitter”,
IEEE Transactions on Circuits and Systems : Regular Papers, October 2007.
(paper) S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, “A 90 microwatt 15-bit Continuous-time Sigma Delta ADC for Digital Audio”,
Proceedings of the European Solid State
Circuits Conference, Munich, September 2007.
(paper) S. Pavan and N. Krishnapura, “Automatic Tuning of Time-Constants in Continuous-Time Delta-Sigma Modulators”,
IEEE Transactions on Circuits and Systems : Express Briefs, April 2007.(paper) K. Reddy and S. Pavan, “Fundamental Limitations of Continuous-time Delta-Sigma Modulators due to Clock Jitter,”
IEEE International Symposium on Circuits and Systems, ISCAS 2006, Kos, Greece, May 2006.
(paper) (slides)