Abstract: A full-duplex transceiver doubles per-pin bandwidth and the aggregate I/O bandwidth of a SoC or ASIC. In full-duplex transceivers, the data is transmitted and received simultaneously in both directions across the channel. The locally transmitted signal and the signal reflected by channel discontinuities contribute to the echo in the received signal. It should be removed from the received signal to recover bits error-free. Echo cancellation in simultaneous bidirectional (SBD) signaling is significantly more challenging in plesiochronous mode with embedded clocking than in mesochronous mode with forwarded or common clocking, since the worst-case echo across the symbol period has to be canceled.

Addressing the challenges in the full-duplex transceivers with embedded clocking or in plesiochronous mode, we present an 8-16 Gb/s/pin full-duplex transceiver with SBD signaling. The transceiver includes an injection-locked clock multiplier, a 0.5 Vpk-pk output-swing voltage-mode transmitter with novel background output impedance calibration, and a digital clock and data recovery. It incorporates both analog echo cancellation via a continuous-time linear equalizer and digital echo cancellation using a digital-to-time converter and a 3-bit DAC. Fabricated in TSMC 65 nm CMOS, SBD signaling at 6.76-14.13 Gb/s/pin with up to 40 Mb/s data rate difference between the two sides is demonstrated in measurements. The recovered clock has an RMS jitter of 5.43-2.25 ps, with sampling time margins of 0.14-0.24 UI at BER <1e-12, and a JTRAN bandwidth of 10.9-5.1 MHz while dissipating 77-101 mW across data rates. Jitter tolerance (JTOL) >1 UIpp at lower frequencies confirms the effectiveness of the echo canceller and clock and data recovery in plesiochronous serial links. The proposed FD-XCVR overcomes the challenges and demonstrates SBD signaling at 2X data rates with low-jitter clock recovery and improved jitter tolerance, while operating with a lower power budget than state-of-the-art designs.

All are cordially invited.

Event Details
Title: An 8-16 Gb/s/pin Full-Duplex Wireline Transceiver With Embedded Clock Recovery
Date: May 15, 2026 at 10:00 AM
Venue: Google Meet (meet.google.com/ief-gbht-vru)
Speaker: Mr. RITAVASH DAS (EE21S024)
Guide: Dr. Saurabh Saxena
Type: MS seminar

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