Active DC Bias Elimination in SiC-Based Dual Active Bridge and MVDC-DAB Realization using series connected Devices

Abstract: In this work, two distinct studies are proposed. The first study addresses high frequency transformer saturation issues in the Dual Active Bridge (DAB) converter, an isolated DC-DC topology that is increasingly adopted in power electronics applications. Silicon Carbide (SiC) based DAB converters are widely preferred for achieving high efficiency with an extremely low DC resistance of the transformer. The high frequency transformer, a key component of the DAB, is susceptible to saturation for any DC voltage. Several factors contribute to the emergence of DC bias current, including mismatches in device forward characteristics, unequal dead-time distribution, variations in gate signal propagation delays, low-frequency AC components in the DC-link voltage, and asymmetrical parasitic inductances in PCB traces. Under such conditions, even a small voltage imbalance arising from static and dynamic mismatches in SiC switches can generate a net DC bias current within the circuit. This phenomenon, although seemingly subtle, has significant consequences. The persistent DC bias current gradually leads to the saturation of the transformer, impacting the overall performance. When the Transient DC Bias Current (TDCBC) becomes significant, the operating flux of the transformer shifts into the nonlinear region of the B-H curve, leading to saturation. To mitigate this issue, the work proposes an active closed loop control strategy for eliminating TDCBC by dynamically adjusting the converter dead time. The method also enables detection of asymmetry using converter current measurements, eliminating the need for complex core flux sensing techniques. The proposed algorithm adjusts dead time in fine steps of 8 ns, up to a maximum of 100 ns, and is implemented using FPGA-based control hardware for precise and efficient operation.

The second study focuses on the growing need for Medium Voltage Dual Active Bridge (MV-DAB) converters in Medium Voltage DC (MVDC) applications. While the DAB topology is well established for DC voltage levels ranging from 48 V to 800 V using 1.2 kV and 1.7 kV devices, there is an increasing demand to extend its application to MVDC systems operating in the 3.3 kV to 10 kV range. This demand is driven by emerging applications such as solid-state transformers, strategic power systems, renewable energy integration and fast charging infrastructure for electric mobility. Currently, multilevel modular converter topologies are commonly employed to realize MV-DAB. In this work, a simplified MVDC-DAB architecture is proposed based on series connected SiC devices within a conventional two level converter framework. In the MVDC side, multiple SiC switches are connected in series in both the upper and lower arms of each phase leg. The number of series connected devices can be scaled based on the target MVDC operating level. The remaining power circuit follows the conventional DAB structure. The LV side employs a single stage two-level converter designed to handle DC voltages in the 48-800V range. The remaining power circuit follows the conventional DAB structure. Therefore, the focus of this work is on the MVDC side converter design. A major challenge in this approach to achieve uniform voltage distribution among the series connected devices during switching transients, especially at turn-off. To overcome this, the proposed work introduces Active Gate Driver (AGD) based voltage balancing techniques to ensure reliable operation of the series connected SiC devices. The AGD employs multiple switched current and voltage stages that dynamically controls the gate charge during the turn-off interval. This control is continuously adjusted based on the drain-to-source voltage of each device in every switching cycle, enabling effective voltage balancing under both steady state and transient conditions.

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Event Details
Title: Active DC Bias Elimination in SiC-Based Dual Active Bridge and MVDC-DAB Realization using series connected Devices
Date: May 11, 2026 at 11:00 AM
Venue: Google Meet (https://meet.google.com/ifm-udgv-ysv)
Speaker: Mr. Ganesan P (EE15D039)
Guide: Dr. Kamalesh Hatua
Type: PHD seminar