Abstract: The computational and memory-access demands of edge AI inference workloads have intensified interest in non von-Neumann paradigms, particularly Compute-In-Memory (CIM) architectures that mitigate data-movement bottlenecks. This work presents an SRAM based hybrid compute-in-memory (CIM) macro with reconfigurable output precision of 5 to 8 bits, targeting the accuracy-energy efficiency tradeoff in neural network inference. A compact hybrid cell enables accurate time-domain computation and efficient charge-domain computation through shared circuitry. Digitization is achieved using an 8-bit fine-coarse time-to-digital converter (TDC) for the time domain, which is reused via a voltage-to-time converter (VTC) in the charge domain, enabling a compact and scalable macro design. A referencing strategy within the TDC reduces oscillator usage and improves energy efficiency by 10–22%. Global PVT variations across the hybrid compute cell, oscillator, VTC, and TDC are addressed through static calibration, while local mismatch in the compute cell and oscillator is corrected via a dedicated calibration technique. Temperature drift is compensated through slope correction using a dedicated delay line that tracks the MAC output shift, covering a range of to in simulation and confirmed at and in measurement. Layer-specific hybrid computation exploiting information deficit is employed to further utilize the accuracy-efficiency tradeoff. Fabricated in a 28-nm process, the prototype achieves 208-711 1b- tera-operations per second per watt (TOPS/W) at 0% sparsity, scaling up to 909 1b-TOPS/W with increasing sparsity. The proposed design achieves accuracy comparable to the software baseline on MNIST (98.86%), CIFAR-10 (91.98%), and CIFAR-100 (68.2%).

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Event Details
Title: Hybrid 28nm SRAM time-charge CIM macro for precise, variation tolerant and energy efficient computation
Date: April 30, 2026 at 09:00 AM
Venue: ESB 244
Speaker: Mr. Daware Prathamesh Mahipati (EE23S019)
Guide: Dr. Janakiraman Viraraghavan
Type: MS seminar

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