Integrated Circuits and Systems group, IIT Madras

EE6332: Modelling and Optimization in VLSI (Jan 2023)

Instructors

Classroom

ESB 129

Schedule

Live session: K-slot - W (3:30 - 4:45 PM) and F(2:00 - 3:15 PM)

Evaluation

  • Mid Term: 20%
  • Project : 40%
  • End Semester Exam: 40%

Course Contents

  • Statistical Compact Model Extraction
  • Gate Sizing via Geometric Programming
  • Machine Learning in EDA

Board Learning Objectives

(What the students should be able to do after the course)

  • Casting a problem in VLSI in a mathematical form.
  • Formulating an optimization problem, proposing a suitable objective function and associated constraints.
  • Solving the problem with commercial solvers.
  • Interpreting the obtained solution and verifying correctness of the same.

Specific Learning Objectives

  • To set up the Linear Back Propagation of Variance problem.
  • Employ importance sampling to estimate rare event failures in circuits
  • To approximate the delay of a logic gate using the logical effort delay model.
  • To set up and solve the path based timing problem.
  • To set up the node based gate-sizing formulation as a Geometric Program.
  • To solve the gate sizing problem using a commercial solver in Python.
  • To obtain greedy approximations for the discrete gate sizes to the continuous solution.

Week 1

  • Review of Level-1 SPICE model - Definition of Idlin, Idsat, Vtlin and Vtsat
  • Introduction to process variations

Week 2

  • Statistical Compact Model Extraction
  • Forward and Back propagation of variance
  • Modeling Ioff and Non-linear optimization

Week 3

  • Conventional Monte Carlo

Week 4

  • Importance Sampling

Week 5

  • Review of RC model of gate delay
  • Logical effort model for delay
  • Path delay optimization - Capacitance as variables

Week 6

  • Buffering Insertion
  • Path delay optimization - Gate size as variables

Week 7

  • Power in Digital Circuits
  • Introduction to Geometric Programming- Monomials and Posynomials

Week 8

  • Static Timing Analysis (STA)
  • Minimum Area Gate Sizing Problem Formulation (Node Based)
  • Gate sizing as a GP
  • Circuit timing wall

Week 9

  • Alternate formulations including minimum area and power

Week 10

  • The continuous solution and convexity
  • Discretizing the continuous solution
  • Timing slack propagation
  • Gate downsizing based on available slack

Week 11

  • Introdcution to Machine Learning- Linear Regression and Gradient Descent
  • Overfitting, cross-validation
  • Constrained K-Means Clustering

Week 12

  • Application of K-Means Clustering for Scan Chain Optimization
  • Overview of reinforcement learning
  • Ensemble techniques