Integrated Circuits and Systems group, IIT Madras

EE6322: VLSI Broadband Communication Circuits(Jan-May 2019)

Instructor

Classroom

  • ESB314B

Schedule

C slot(Mo 10am; Tu 9am; We 8am; Fr 12pm)

Course page on moodle

Registered students can login and see the course page at https://courses.iitm.ac.in/. Resources, tutorials, exam schedules, discussion forum etc. can be accessed from the moodle page.

Teaching Assistants

Login to moodle at https://courses.iitm.ac.in/ to post questions and contact TAs and faculty.

Evaluation

  • Assignments(20%)
  • Final Project(30%)
  • Presentation(10%)
  • Mid-sem exam (20%)
  • End-sem exam(20%)

Recorded lectures

The recorded lectures are available here. You can also find lectures from previous years at the same link. The NPTEL online course Analog Circuits also covers a portion of the material.

Assignments

Assignments will be posted below. You are expected to solve them on your own. You should submit each one by 1155pm of the due date mentioned. Copying will carry strict penalties.

Course contents

Digital communication over wired links; Mesochronous and Plesiochronous links; Clock and data recovery circuits for these links; Phase detectors for periodic signals and random data; Phase-locked loop and delay locked loop; Analog and digital implementations of CDRs and PLLs; Channel characteristics-intersymbol interference, eye diagrams; Linear equalization at the transmitter and receiver; Decision feedback equalization; Equalizer adaptation using the LMS algorithm.

Objectives

To understand and carry out simulations of CDR and PLL circuits, channel models, and equalizers; To be able to determine the parameters of these systems starting from specifications.

References

Pre-requisites

  • Basics of continuous-time and discrete-time signals and systems; Basics of transmission lines; Knowledge of MOS transistor basics related to circuit design, small signal equivalent circuits, small and large signal analysis; Design of building blocks-basic amplifier stages, differential pairs, and bias generators;

Attendance

Attendance will be strictly enforced and those falling short will not be permitted to write the end sem exam. TAs will go around the room taking attendance at the beginning of the class. If you are more than 5 min. late, please do not enter the classroom.