NT Alexander Institute Chair Professor

Department of Electrical Engineering

Indian Institute of Technology, Madras

Chennai, 600036, India

Tel: +91-44-22574437

email: shanthi at ee dot iitm dot ac dot in

- S.Pavan, T. Halder and A.Kannan, ``Continuous-time Incremental Delta-Sigma Modulators with FIR Feedback"
*IEEE Transactions on Circuits and Systems: Regular Papers*, to appear. - S.Manivannan and S.Pavan, ``A 65nm CMOS Continuous-Time Pipeline ADC achieving 70dB SNDR in 100MHz Bandwidth"
*IEEE Solid-State Circuits Letters*, May 2021. - A.Baluni and S.Pavan, ``Analysis and Design of a 20 MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback "
*IEEE Journal of Solid-State Circuits*, March 2021. - S.Pavan and H.Shibata, ``Continuous-time Pipelined Analog-to-Digital Converters: A Mini-Tutorial"
*IEEE Transactions on Circuits and Systems: Express Briefs*, March 2021. - S.Manivannan and S.Pavan, ``Improved Continuous-Time Delta-Sigma Modulators with Embedded Active Filtering"
*IEEE Transactions on Circuits and Systems: Regular Papers*, October 2020. - S.Billa, S.Dixit and S.Pavan, ``Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator"
*IEEE Journal of Solid State Circuits*, October 2020. - R.Theertham, P.Koottala, S.Billa and S.Pavan, ``Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density "
*IEEE Journal of Solid State Circuits*, September 2020. - S.Javvaji, V.Singhal, V.Menezes, R.Chauhan and S.Pavan, ``Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting "
*IEEE Journal of Solid State Circuits*, September 2019. - R.Theertham and S.Pavan, ``Improved Offline Calibration of DAC Mismatch Errors in Delta Sigma Data Converters ,"
*IEEE Transactions on Circuits and Systems: Express Briefs*, October 2019. - R.Theertham and S.Pavan, ``Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators ,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, August 2019. - K.Datta and S.Pavan, ``Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters ,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, August 2019. - S.Pavan, ``An Alternative Approach to Bode's Noise Theorem ,"
*IEEE Transactions on Circuits and Systems: Express Briefs*, May 2019. - S. Manivannan and S.Pavan, ``Degradation of Alias Rejection in Continuous-Time Delta Sigma Modulators by Weak Loop-Filter Nonlinearities ,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, October 2018. - S.Pavan and E.Klumperink, ``Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, October 2018. - S.Pavan, ``Improved Chopping in Continuous-time Delta-Sigma Modulators using FIR Feedback and N-path Techniques,"
*IEEE Transactions on Circuits and Systems: Express Briefs*, May 2018. - S.Pavan and E.Klumperink, ``Analysis of the Effect of Source Capacitance and Inductance on N-Path Mixers and Filters,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, May 2018. - A.Jain and S.Pavan, ``Continuous-time Delta-Sigma Modulators using Time-Interleaved FIR Feedback,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, February 2018. - H.Shibata, V.Kozlov, Z.Ji, A.Ganesan, H.Zhu, D. Paterson, J.Zhao, S.Patil and S.Pavan,``A 9 GS/s 1.125 GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164 dBFS/Hz NSD,"
*IEEE Journal of Solid-State Circuits*, December 2017. - S.Billa, A.Sukumaran and S.Pavan,``Analysis and Design of Continuous-time Delta-Sigma Modulators Incorporating Chopping,"
*IEEE Journal of Solid-State Circuits*, September 2017. - S.Pavan and E.Klumperink, ``Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, to appear, 2017. - N.Sinha, M.Rachid, S.Pavan and S.Pamarti ``Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components,"
*IEEE Journal of Solid State Circuits*, August 2017. - S.Pavan, ``Analysis of Chopped Integrators and its Application to Continuous-time Delta Sigma Modulator Design,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, August 2017. - A.Sukumaran and S.Pavan, ``Continuous-time Delta Sigma Modulators with Dual Switched Capacitor Return-to-Zero DACs ,"
*IEEE Journal of Solid State Circuits*, July 2016. - J. de la Rosa, R.Schreier, K.P.Pun and S.Pavan, ``Next-generation Delta-Sigma Converters : Trends and Perspectives,"
*IEEE Journal of Emerging Topics in Circuits and Systems*, December 2015. - A.Sukumaran and S.Pavan, ``Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback,"
*IEEE Journal of Solid State Circuits*, November 2014. - R.S.Rajan and S.Pavan, ``Design Techniques for Continuous-Time Delta Sigma ADCs with Embedded Active Filtering"
*IEEE Journal of Solid State Circuits*, October 2014. - S.Pavan and R.S.Rajan, ``Simplified Analysis and Simulation of the STF, NTF and Noise in CTDSMs,"
*IEEE Transactions on Circuits and Systems: Express Briefs*, Sept. 2014. - S.Pavan and R.S.Rajan, ``Interreciprocity in linear periodically time varying networks with sampled outputs,"
*IEEE Transactions on Circuits and Systems: Express Briefs*, Sept. 2014. - N.Rajesh and S.Pavan, `` Design of Lumped Component Programmable Delay Elements for Ultra-Wideband Beamforming,"
*IEEE Journal of Solid State Circuits*, August 2014. - S.Pavan, ``Continuous-time Delta Sigma Modulator Design using the Method of Moments,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, June 2014. - A.Jain and S.Pavan, ``Continuous-time Delta Sigma Modulators with Enhanced Linearity and Reduced Clock Jitter Sensitivity using the Switched Capacitor Return to Zero DAC,"
*IEEE Transactions on Circuits and Systems: Regular Papers*, May 2014. - T.Nandi, K.Boominathan and S.Pavan, ``Continuous-time Delta Sigma Modulators with Enhanced Linearity and Reduced Clock Jitter Sensitivity using the Switched Capacitor Return to Zero DAC,"
*IEEE Journal of Solid State Circuits*, August 2013. - M.S.Veeramani, P.Shyam, N.Ratchagar,A.Chadha, E.Bhattacharya and S.Pavan,``A Miniaturized pH Sensor With an Embedded Counter Electrode and a Readout Circuit,"
*IEEE Sensors Journal*, May 2013. - S.Pavan,``A Time Domain Perspective of the Signal Transfer Function of a Continuous-time Delta Sigma Modulator,"
*IEEE Transactions on Circuits and Systems : Express Briefs*, February 2013. - P.Shettigar and S.Pavan,``Design Considerations for Wideband Single Bit Delta Sigma Modulators with FIR Feedback DACs
*IEEE Journal of Solid State Circuits*, December 2012. - R.S.Rajan and S.Pavan,``Device Noise in Continuous Time Oversampled Converters,"
*IEEE Transactions in Circuits and Systems,*September 2012. - V.Singh, N. Krishnapura, S.Pavan, B.Vigraham, D.Behera and N. Nigania,``A 16 MHz BW 75 dB Dynamic Range CT Delta Sigma ADC Compensated for more than one Cycle Excess Loop Delay,"
*IEEE Journal of Solid State Circuits,*August 2012. - A. Jain, M. Venkatesan and S.Pavan,``Design and Analysis of a High Speed Continuous Time Delta Sigma Modulator using the Assisted Opamp Technique,"
*IEEE Journal of Solid State Circuits,*July 2012. - S. Thyagarajan, S. Pavan and P.Sankar,``Active filters using the Gm-assisted OTA-RC technique",
*IEEE Journal of Solid State Circuits,*July 2011. - S. Pavan, ``On continuous-time Delta Sigma modulators with Return-to-Open DACs",
*IEEE Transactions on Circuits and Systems : Express Briefs,*May 2011. - S. Pavan, ``Alias rejection of continuous-time oversampling converters with switched-capacitor feedback DACs",
*IEEE Transactions on Circuits and Systems : Regular Papers,*February 2011. - V. Singh, N. Krishnapura and S. Pavan, ``Compensating for quantizer delay in excess of one clock cycle in continuous-time Delta-Sigma modulators",
*IEEE Transactions on Circuits and Systems : Express Briefs,*September, 2010. - S. Pavan, ``Efficient simulation of weak nonlinearities in continuous-time oversampling converters",
*IEEE Transactions on Circuits and Systems : Regular Papers,*August 2010. (paper) - S. Pavan and P. Sankar, "Power reduction in continuous-time Delta-Sigma modulators using the assisted opamp technique",
*IEEE Journal of Solid State Circuits,*July 2010. (paper) - K. Reddy and S.Pavan, "A power efficient continuous time Sigma-Delta modulator with 15 MHz bandwidth and 70 dB dynamic range",
*Analog Integrated Circuits and Signal Processing,*June 2010. (paper) - S. Pavan, "Systematic design centering of continuous-time oversampling converters",
*IEEE Transactions on Circuits and Systems : Express Briefs,*March 2010 (paper) - T.Laxminidhi,V.Prasadu and S.Pavan, ``Widely Programmable High Frequency Active-RC Filters in CMOS Technology",
*IEEE Transactions on Circuits and Systems I : Regular Papers,*(paper) February 2009. - S.Pavan, ``Excess Loop Delay Compensation in Continuous-time Delta Sigma Modulators",
*IEEE Transactions on Circuits and Systems II : Express Briefs, November 2008.(paper).* - S. Pavan, ``Power and Area Efficient Adaptive Equalization at Microwave Frequencies",
*IEEE Transactions on Circuits and Systems I : Regular Papers,*July 2008.(paper) - S. Pavan, N. Krishnapura, R. Pandarinathan and P. Sankar, ``A Power Optimized Continuous-time Delta-Sigma Modulator for Audio Applications,"
*IEEE Journal of Solid State Circuits*, February 2008.(paper) - P. Sankar and S. Pavan,``Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators",
*IEEE Transactions on Circuits and Systems : Express Briefs*, December 2007.(paper) - K. Reddy and S. Pavan, ``Fundamental Limitations of Continuous-time Delta Sigma Modulators due to Clock Jitter",
*IEEE Transactions on Circuits and Systems : Regular Papers*, October 2007.(paper) - S. Pavan and T. Laxminidhi, ``Accurate Characterization of Integrated Continuous Time Filters",
*IEEE Journal of Solid State Circuits, August 2007.(paper)* - T. Laxminidhi and S. Pavan,``Efficient Design Centering of High Frequency Continuous Time Filters",
*IEEE Transactions on Circuits and Systems : Regular Papers, July 2007.(paper)* - S. Pavan and N. Krishnapura, ``Automatic Tuning of Time-Constants in Continuous-Time Delta-Sigma Modulators",
*IEEE Transactions on Circuits and Systems : Express Briefs, April 2007.(paper)* - S. Pavan and R. Tiruvuru, ``Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers"
*IEEE Transactions on Circuits and Systems : Regular Papers, February 2007. (paper)* - V. Srinivas, S. Pavan, A. Lachhwani and N. Sasidhar,`` A Distortion Compensating Flash Analog to Digital Conversion Technique,"
*IEEE Journal of Solid State Circuits*. September 2006. (paper) - S. Pavan and S. Shivappa,``Nonidealities in Traveling Wave and Transversal FIR Filters Operating at Microwave Frequencies",
*IEEE Transactions on Circuits and Systems : Regular Papers*, January 2006. (paper) - S. Pavan, M. Tarsia, S. Kudszus and D. Pritzkau,`` Design considerations for Integrated Modulator Drivers in SiGe Technology",
*International Journal of High Speed Electronics and Systems*, September 2005. - S. Pavan, ``Continuous-Time Integrated FIR Filters at Microwave Frequencies",
*IEEE Transactions on Circuits and Systems-II, Analog and Digital Signal Processing*, January 2004. (paper) - K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, ``A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-um digital CMOS process",
*IEEE Journal of Solid State Circuits,*December 2000. - S. Pavan and Y. Tsividis, ``Time Scaled Electrical Networks - Properties and Applications in the Design of Programmable Analog Filters", IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, , Vol. 47, No.2, pp. 161-5, February 2000.(paper)
- S. Pavan, Y. Tsividis and K. Nagaraj, `` Widely Programmable High Frequency Continuous Time Filters in Digital CMOS Technology", IEEE Journal of Solid State Circuits,, Vol. 35, No.4, April 2000.(paper)
- S. Pavan and Y. Tsividis, ``An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning'', IEEE Transactions on Circuits and Systems-I, vol. 45, no. 9, pp. 1242-1249, May 1998. (paper)

- K.Singh and S.Pavan, ``A 14 bit dual channel incremental continuous-time Delta Sigma modulator for multiplexed data acquisition,"
*IEEE International Conference on VLSI Design}, pages 1--5.*IEEE, 2016. - S.Billa, A.Sukumaran, and S.Pavan, ``A 280uW, 24kHz BW, 98.5dB SNDR, chopped single-bit CTDSM achieving less than 10 Hz 1/f noise corner without chopping artifacts,"
*IEEE International Solid State Circuits Conference (ISSCC)*, pages 1--2. IEEE, 2016. - A.Sukumaran and S.Pavan, ``A continuous-time Delta Sigma modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC,"
*Proceedings of the European Solid-State Circuits Conference (ESSCIRC)},*pages 217--220. IEEE, 2015. - N.Rajesh and S.Pavan, ``Programmable analog pulse shaping for ultra-wideband applications,"
*IEEE International Symposium on Circuits and Systems (ISCAS)},*pages 461--464. IEEE, 2015. - N.Rajesh and S.Pavan, ``Improved characterization of differential multi-GHz integrated amplifiers and filters,"
*Proceedings of the IEEE International Microwave Symposium,*pages 461--464. IEEE, 2015. - S.Krishnan and S.Pavan, ``A 10 Gbps eye opening monitor in 65nm CMOS,"
*IEEE International Symposium on Circuits and Systems (ISCAS)},*pages 3028--3031. IEEE, 2015. - R.Rajan and S.Pavan, ``A 5mW CT Delta Sigma ADC with embedded second order active filter and VGA achieving 82dB dynamic range in 2MHz bandwidth,"
*2014 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC)},*pages 156--158, 2014. - S.Pavan, `` Efficient estimation of the signal and noise transfer functions of a continuous time Delta Sigma modulator,"
*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS),*Melbourne, pages 1--4, 2014. - M.Veeramani, N.Ratchagar, E.Bhattacharya, S.Pavan, S.Prakash, and A.Chadha, ``Compact silicon biosensor for the clinical range estimation of blood serum triglyceride,''
*IEEE SENSORS*, pages 1--4. IEEE, 2013. - A.Sukumaran and S.Pavan, ``A 280uW audio continuous-time Delta Sigma modulator with 103 dB DR and 102 dB A-Weighted SNR,"
*Proceedings of the Asian Solid State Circuits Conference, Singapore*, pages 1--4, 2013. - A.Sukumaran, K.Karanjkar, S.Jhanwar, N.Krishnapura, and S.Pavan, "A 1.2V 285uA analog front end chip for a digital hearing aid in 0.13um CMOS,"
*Proceedings of the Asian Solid State Circuits Conference, Singapore*, pages 1--4, 2013. - N.Rajesh and S.Pavan, "A lumped component programmable delay element for ultra-wideband beamforming,"
*Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), San Jose, California*, pages 1--4, 2013. - A.Jain and S.Pavan, "Efficient characterization of continuous time oversampling converters using a duobinary test interface,"
*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS),*Beijing pages 1--4, 2013. - P.Shettigar and S.Pavan, "A 15mW 3.6 GS/s CT-Delta Sigma ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS, "
*IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC),*pages 156--158, 2012. - R.S. Rajan and S.Pavan, "Device noise in continuous-time $\Delta$$\Sigma$ modulators with Switched-Capacitor feedback DACs,"
*2012 IEEE International Symposium on Circuits and Systems (ISCAS)*, pages 524--527, 2012. - T.Nandi, K.Boominathan, and S.Pavan, "A continuous-time Delta Sigma modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC,"
*Proceedings of the IEEE Custom Integrated Circuits Conference (CICC)*, pages 1--4, 2012. - A. Jain, M. Venkateswaran and S. Pavan, "A 4mW 1GS/S continuous-time Delta Sigma modulator with 15.6 MHz bandwidth and 67 dB dynamic range ",
*Proceedings of the IEEE European Solid State Circuits Conference,*Helsinki, Finland, September 2011. - V. Singh, N. Krishnapura, S. Pavan, B. Vigrah am, D. Behera and N. Nigania, "A 16MHz BW 75dB DR CT DS ADC Compensated for More Than One Cycle Excess Loop Delay ",
*Proceedings of the IEEE Custom Integrated Circuits Conference,*San Jose, California, September 2011. - S. Pavan, "The inconvenient truth about alia s rejection in continuous-time oversampling converters",
*Proceedings of the IEEE International Symposium on Circuits and Systems,*Rio de Janeiro, Bra zil, May 2011. - S. Thyagarajan, S. Pavan and P.Sankar, "Low distortion active-filters using the Gm-assisted Active-RC technique",
*Proce edings of the European Solid State Circuits Conference,*Seville, Spain, Se ptember 2010. - S. Pavan, "Understanding weak nonlinearities in continuous-time oversampling converters",
*IEEE International Symposium on Circuits and Systems (ISCAS),*Paris, May 2010. - S.Pavan and P.Sankar, "A 110-microwatt Single Bit Audio Continuous-time Oversampled Converter with 92.5 dB Dynamic Range",
*European Solid State Circuits Conference (ESSCIRC),*Athens, Greece, September 2009 (paper). - Y.Darhwekar, R.Kumar, D.Sahu, S.Pavan, A.Lacchwani and S.Mukherjee, "A Digitally Assisted Baseband Filter with 9 MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain",
*International Symposium on Circuits and Systems (ISCAS),*Taipei, Taiwan, 24-27 May 2009.(paper) - S.Saxena,P.Sankar and S.Pavan, "Automatic Tuning of Time Constants in Single-bit Continuous-time Delta Sigma Modulators",
*International Symposium on Circuits and Systems (ISCAS),*Taipei, Taiwan, 24-27 May 2009. (paper) - V.Hareesh, S.Pavan and E.Bhattacharya, "Readout Circuit Design for an EISCAP Biosensor",
*IEEE Biomedical Circuits and Systems Conference,*November 2008.(paper) - K. Reddy and S.Pavan, "A 20.7 mW Continuous-Time Delta-Sigma Modulator with 15 MHz Bandwidth and 70dB Dynamic Range",
*Proceedings of the European Solid State Circuits Conference, Edinburgh*, September 2008.(paper) - S. Pavan, "Power and Area Efficient Analog Adaptive Equalization",
*IEEE International Symposium on Circuits and Systems (ISCAS)*, Seattle, May 2008.(paper) - T. Laxminidhi, V. Prasadu and S. Pavan, "A Low Power 44-300 MHz Programmable Active-RC Filter in 0.18um CMOS",
*Proceedings of the Custom Integrated Circuits Conference*, San Jose, September 2007.(paper) - S. Pavan, N. Krishnapura, R. Pandarinathan and Prabu Sankar, "A 90 microwatt 15-bit Continuous-time Sigma Delta ADC for Digital Audio",
*Proceedings of the European Solid State Circuits Conference*, Munich, September 2007.(paper) - T. Laxminidhi and S. Pavan, "Efficiently Design Centering High Frequency Integrated Continuous-time Filters",
*IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans(paper)* - S. Pavan, "Singly Terminated Transmission Line Filters for High Speed Adaptive Equalization",
*IEEE International Symposium on Circuits and Systems, ISCAS, May 2007, New Orleans.(paper)* - S. Pavan and T.Laxminidhi, " A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters," Proceedings of the
*IEEE Custom Integrated Circuits Conference*, CICC 2006, San Jose, September 2006.(paper) - S. Pavan and T.Laxminidhi, " A 70-500 MHz Programmable CMOS Filter Compensated for MOS Nonquasistatic Effects," Proceedings of the
*IEEE European Solid State Circuits Conference*, ESSCIRC 2006, Switzerland, September 2006. (paper) - S. Murali and S. Pavan," Rapid Simulation of Current Steering DACs using Verilog-A," Proceedings of the
*IEEE Custom Integrated Circuits Conference*, CICC 2006, San Jose, September 2006.(paper) - A. Sharma and S. Pavan,"A Single Inductor Multiple Output Converter with Adaptive Delta Current Mode Control,"
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) - K. Reddy and S. Pavan,"Fundamental Limitations of Continuous-time Delta-Sigma Modulators due to Clock Jitter ,"
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides) - T. Rajesh and S. Pavan, "Transmission Line based FIR Structures for High Speed Adaptive Equalization,"
*IEEE International Symposium on Circuits and Systems*, ISCAS 2006, Kos, Greece , May 2006.(paper) (slides) - S. Pavan and S. Shivappa," Analysis of Traveling Wave and Transversal Analog Adaptive Equalizers",
*IEEE International Symposium on Circuits and Systems*, ISCAS 2005, Kobe , May 2005.(paper) (slides) - S. Pavan, " A Fixed Transconductance Bias Circuit for CMOS Analog Integrated Circuits",
*IEEE International Symposium on Circuits and Systems*, ISCAS 2004, Vancouver , May 2004.(paper) (slides) - S. Pavan, " Analog FIR Filters at Microwave Frequencies ",
*Proceedings of the National Conference on Communications*, IIT Madras, Chennai, February 2003.(paper) - G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. Martin, P. Wu and S. Pavan, " A 165 Msps 8 bit CMOS A/D Converter with Background Offset Cancellation ",
*Proceedings of the Custom Integrated Circuits Conference*, May 2001. (paper) - K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A 700 Msps 6 bit Read Channel A/D Converter with 7 bit Servo Mode", International Solid State Circuits Conference, February 2000. (paper)
- K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio and T. R. Viswanathan, " A Dual Mode 700 Msps-6 bit, 200 Msps-7 bit A/D Converter in 0.25u CMOS", Ninth Workshop on Advances in Analog Circuit Design, Tegernsee, Germany , April 2000.
- S. Pavan, Y. Tsividis and K. Nagaraj, " A 60-350 MHz Programmable Analog Filter in a Digital CMOS Process", Proceedings of the European Solid State Circuits Conference,, September 21-23 1999, Duisburg, Germany.(paper, slides)
- S. Pavan, Y. Tsividis and K. Nagaraj, "Modeling of Accumulation MOS Capacitors for Analog Design in Digital VLSI Processes", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 143-146, May 31-June 3 1999, Orlando, Florida.(paper, slides )
- N. Krishnapura, S. Pavan, C. Mathiazhagan, and B. Ramamurthi, "A Baseband Pulse Shaping Method for Gaussian Minimum Shift Keying", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 249-252, Jun 1-3 1998, Monterey, California. (paper, slides)
- S. Pavan and Y. Tsividis, "An Analytical Solution to a Class of Oscillators and its Application to Filter Tuning", IEEE International Symposium on Circuits and Systems, vol. 1, pp. 480-483, Jun 1-3 1998, Monterey, California.(paper)

- Shanthi Pavan and Siva Thyagarajan, "Low distortion filters", US 9,000,389
- Shanthi Pavan, "Power and Area Efficient Adaptive Equalization", US 7,471,751
- Shanthi Pavan, "Distortion Compensation Technique for Flash Type Analog-to-Digital Converters", Europe 1,207,624
- John Wang, Sudeep Bhoja and Shanthi Pavan, "Method and Apparatus for Improved High-speed Adaptive Equalization", US 7,301,997.
- Shanthi Pavan, "Integrated circuit implementation for power and area efficient adaptive equalization", US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California.
- John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao, "Method and apparatus for improved high-speed adaptive equalization", US 7,003,228, Feb. 21, 2006.
- Shanthi Pavan et al.,"Mobility Compensation in MOS Integrated Circuits", US 6,822,505, 23 Nov. 2004.
- Shanthi Pavan et al., "Method and System for Compensation of Low-frequency Photodiode Current in a Transimpedance Amplifier", US 6,552,615, 22 Apr. 2003.
- Shanthi Pavan et al., "Programmable Analog Tapped Delay Line Filter Having Cascaded Differential Delay Cells", US 6,545,567, 8 Apr. 2003.
- Shanthi Pavan, "Fixed Transconductance Bias Apparatus", US 6,400,185, 4 Jun. 2002.
- Shanthi Pavan et al., "Fast Acting Polarity Detector", US 6,369,726, 2 Apr. 2002.
- Shanthi Pavan, "Low Distortion Sample-and-Hold Circuit", US 6,323,697, 27 Nov. 2001.
- Shanthi Pavan, "High Frequency Boost Technique", US 6,304,134, 16 Oct. 2001
- Shanthi Pavan et al., "Method and Apparatus for Tuning High-Q Bandpass Filters using Pulse Excitation", US 5,945,889, 31 Aug. 1999.

- S. Pavan, C. Srinivasan and P. Easwaran, ``System Level Aspects of A/D Converter Designs", half day tutorial at the
*International Conference on VLSI Design,*Hyderabad, India, 2006. - S. Pavan and N. Krishnapura, ``Oversampled Data Converter Design", full day tutorial at the
*International Conference on VLSI Design,*Hyderabad, India, 2008. - K. Balemarthy and S. Pavan, ``Signal Processing for Fiber Optic Communication", half day tutorial at the
*National Conference on Communication,*Bombay, India, 2008. - N. Krishnapura and S. Pavan, ``Negative Feedback Circuit and System Design," full day tutorial at the
*International Conference on VLSI Design,*New Delhi, India, 2009. - S. Pavan, ``Design Techniques for High-Performance Continuous-time Delta Sigma Conversion," half day tutorial at the
*European Solid State Circuits Conference,*Seville, Spain, 2010. - S. Pavan, ``High-Performance Continuous-time Delta Sigma Converters," Educational Sessions of the
*Custom Integrated Circuits Conference,*San Jose, USA, 2010.

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** Solutions Manual : Operation and Modeling of the MOS Transistor (by Yannis Tsividis) **

Mehran Bagheri & Shanthi Pavan

McGraw Hill Publishing Company, New York, NY