Binary neural networks are widely regarded as the hardware-cheapest end of the quantization spectrum, but inside an analog compute-in-memory column running Input-Conditioned Quantization (ICQ) that picture flips. ICQ splits each MAC into a tracked input-conditioned mean and a much narrower residue, presenting only the residue to the pitch-matched column ADC. My thesis shows that the mean-path error gets attenuated by a factor of 2^−(B−1) when B-bit bit-slice MACs are recombined into a dot product a relaxation that multi-bit networks enjoy and binary networks do not, so a binary ICQ deployment actually needs a finer mean quantiser than the residue ADC, while a multi-bit one can get away with a coarser one. To address this asymmetry I propose a fully-digital adder-tree mean tracker that is adjacent to an existing 1024-wordline CIM compute column without requiring a high precision pitch-matched ADC for mean quantization.
Time Domain Compute In Memory architecture borrows the concept of asynchronous operation from analog signal processing while taking advantage of the inherent delay characteristics of the circuit, resulting in energy-efficient operation. It also provides unlimited "Time" accumulation, as opposed to its "Voltage" counterpart, which maintains high accuracy even for larger-length MAC operations. My research is currently focusing on Time Domain CIM hardware design for efficient and accurate AI accelerators
Charge-domain in-memory computing (IMC) utilizes capacitors integrated within the memory array to perform signal accumulation directly in the analog domain, where the total accumulated charge represents the dot-product (MAC) output. Since capacitors are generally less susceptible to device variations, and the operation is inherently digital-like: charge is either transferred or not transferred, the architecture achieves a higher signal-to-noise ratio (SNR) without requiring elaborate calibration schemes. My research focuses on enabling multi-bit dot-product operations in charge-domain IMC while minimizing the energy overhead associated with digitizing the accumulated analog signal.
My research focuses on designing energy-efficient digital SRAM-based compute-in-memory macros for operations such as vector-matrix multiplication and logic-intensive workloads, with an emphasis on improving throughput. I am also interested in studying the computational patterns of emerging neural networks and leveraging those insights to develop novel memory and circuit architectures tailored to their evolving requirements.
My research focuses on energy-efficient compute-in-memory (CIM) and near-memory architectures for next-generation AI workloads, with emphasis on digital and hybrid CIM systems for CNNs, Transformers, and large language models. Current interests include memory-centric accelerator design, systolic and dataflow-aware architectures, sparse and precision-adaptive computing, efficient workload mapping, and scalable hardware acceleration for emerging AI applications. The work explores algorithm-to-hardware co-design approaches that reduce data movement and improve throughput, energy efficiency, and scalability for modern deep neural network inference.
Rohin is from the CSE department and is jointly guided by Prof. Chester Rebeiro from the same department. My research focuses on hardware security, especially power side-channel leakage in cryptographic circuits, with an emphasis on timing-aware pre-silicon leakage estimation and glitch-aware circuit-level mitigation. I develop EDA-based techniques to identify leakage hotspots early in the design flow and to improve side-channel resistance through gate-level analysis, arrival-time control, and secure circuit optimization.
Piyush is jointly guided by Prof. Bijoy Krishna Das from the EE department. My research advances scalable programmable photonic integrated circuits (PICs) through a unified software–hardware co-design approach. I developed PSO-based self-configuration techniques to mitigate fabrication-induced non-idealities, scaling programmable meshes from 4×4 MZI architectures to 14-MZI recirculating networks. I also introduced diode-assisted programmable phase shifters that reduce bondpad complexity and power consumption by 50%, validated in microwave photonics and Quantum Random Number Generation (QRNG). Currently, I am exploring multipurpose programmable photonic processors, envisioned as Field-Programmable Photonic Gate Arrays (FPPGAs), enabling diverse photonic functionalities on a unified re-configurable silicon photonic platform.
Alumni
Name
Research
Description
Karthikeyan. M, MS (2022).
Karthikeyan is currently with IBM India Pvt. Ltd. in the Processor Design group. You can read about his Glitch minimization work using Geometric Programming here.
Ashwin is currently with Intel India in the Processor Architecture and Research Labs. Dynamic range of the ADC in Compute In-Memory (CIM) is tailored to the range of the MAC over all inputs in a dataset. However, only one input is presented at a time to the CIM accelerator. My work focusses on tailioring the input range of the ADC to the conditional distribution, conditioned on the input. Tracking the mean is the key challenge in this problem. You can read more about my work here.
Balaji is currently with PIMIC doing compute-in-memory.
In compute-in-memory (CIM) macros, integrating high-precision (>7-bit) analog-to-digital converters (ADCs) with the memory array significantly increases area and energy costs. However, by exploiting the fact that only one input vector is presented to the CIM accelerator at any given time, we can use the reduced input-conditioned MAC range to achieve greater quantization precision than the on-chip ADC's native resolution. My research focuses on the design of a CIM macro chip with the central block being a cascode current mirror-based subtract and amplify circuit that enables tracking the input conditioned MAC range, giving up to 10-b precision with a 7-b on-chip ADC. For more details of my work, please refer here.
Sonu is currently with Samsung Semiconductors India Research.
SOI technology has been in the mainstream for high performance microprocessor design as it offers numerous advantages over conventional bulk CMOS. However, the technology suffers from significant self-heating issues due to its design. The focus of my research is to model the heat flow in interconnects for SOI devices for circuit simulators to accurately predict the performance and reliability of a circuit.
