Table of Contents
Updates
List of Tasks with current status
| Tasks | status | comments/issues |
|---|---|---|
| Architecture Design: Study of trade-offs specific for the application | Trade-offs listed | Architecture trade-off list |
| Architecture Design: ADC top-level architecture/specs proposal | A new architecture proposed | Proposed architecture details, 1)The LP filter may not be adopted, 2)To initially look at modulator without feedforward flash |
| Architecture Design: Choice of Modulator architecture/specifications | Initial choice done | Modulator spec details 1) To go forward with the Single-Bit modulator |
| Architecture Design: choice of topology CIFF/CIFB or CIFF-CIFB | A Composite topology proposed | Modulator topology details |
| Architecture Design: Getting CT equivalent and Excess loop delay compensation, choice of DAC waveform | done | Model-level simulation detailsModel-level simulation details |
| Architecture Design: evaluating NTF & MSA with RC variations, excess loop delay | - | Architecture-level design details |
| Model-level evaluation: Building models and evaluating the Modulator performance with non-idealities | - | Model-level simulation details |
| Circuit Architecture Design: Define the architectures for OTAs,DAC and Comparators | - | Circuit details |
| Re-optimize Architecture: Re-optimize the Modulator Architectures based on Circuit architectures | - | - |
| Circuit Design: Design the Circuits for all the individual blocks | - | - |
| Top-Level evaluation: Evaluate the top-level performance | - | - |
| Layout: Layout design of the blocks and top-level | - | - |
| Post-Layout evaluation: Post-Layout evaluations of the individual blocks | - | - |
Architecture-level design details
Choice of Architecture
Proposed Architectures
Sigma-delta modulator with Feedforward Flash Architecture
Modulator Topology
- For choosing modulator following points are considered:
- The first-integrator doesnt come in fastest path.
- There is no need for separate summing amplifier.
- There is only integrator4 in the fastest path. So it is a lot kinder on excess-loop delay problem.
- The first-integrator cap is not too huge, say < 5pF
- Minimum no of DAC feedbacks.
Design methodology:
- First the modulator is implemented in discrete-time CIFB topology using sigma-delta toolbox. This structure has the final-integrator in the fastest path, while the first-integrator in the slowest path. This architecture has Nth order low-pass STF which is the most desirable STF. The demerits in this architecture is that it needs N number of DAC feedback points and its first-integrator gain is too small which needs it to have huge integrating caps.
- The discrete-time CIFB topology is mapped to continuous-time. The (N-1)stages of it is converted in to CIFF stage with final integrators input node as summing node. This firstly, puts the first integrator in the second fastest path and hence the its cap requirement will be greatly reduced. Secondly, the no of DAC feedback points are reduced to 2. Unfortunately now the STF is screwed up since it will have a peaking near the STF cutoff frequency.
- To get back the Nth order Low-pass STF as in CIFB, the feedforward inputs are given to the CIFF stage. The feedforward input coefficients b2' and b3' are calculated to cancel the (N-2)th order and (N-1)th order signal paths, leaving behind only the Nth order signal path.
- Finally, node scaling is done if necessary.
Feedback Filter
- Ways to introduce filters:
- Method1: Introducing a pole (s-domain) just before the integrator and compensating with a zero in the loop filter. The poles can be introduced by using the input resistors and huge caps. Compensation zero can be introduced in the loop filter by multiple ways.
- Method2: Introducing a digital filter after the quantizer, and an inverse Z-domain (switch-cap) filter before the quantizer.
- Advantages:
- The power requirement in the integrator1 amp for reducing distortion will reduce. Integrator1 may now have to target only noise problem.
- Jitter may be reduced using switch-cap filter implementation without any power penalty associated with switch-cap feedback.
- Disadvantages:
- In method1, the requirement of huge caps would restrict its usability to only very high frequency applications.
- In method2, since we use a switch cap filter before the quantizer we will have additional switching powerloss.
Model-level simulation details
- Details of the initial model-level architecture evaluations, effect of excess-loop delay, NRZ/RZ DAC —> model-level_results.pdf
- Excess-loop delay compensation:
- The loop filter, H(s) = ∑ Pn*s^(-n) , where n= 1 to 4 ;
- Pn coefficients obtained from Matlab (using d2c function): P4 = 7.8e-3, P3 = 0.068 , P2 = 0.283 , P1 = 0.72
- The loop is compensated for 50% excess delay considering RZ DAC using 'S-domain compensation method' .
- Pn coefficients after excess-loop delay compensation: P4 = 7.8e-3, P3 = 0.072 , P2 = 0.318 , P1 = 0.87
- Modulator Coefficients in the simplest form:
| Integrator UGB/Fs : | c1 = 0.39 , c2 = 0.24 , c3 = 0.11 , c4 = 0.72 |
|---|---|
| Feedback coefficients: | a1 = 1 , a4 = 1 |
| Integrator feedforward coefficients: | a2 = 1 , a3 = 1 |
| Input feedforward coefficients: | b1 = 1 , b2 = -3.37 , b3 = -3.66 |
- The two complex zero pairs are introduced in the signal-Band of the NTF to get optimum SNR.
- NTF with/without excess-delay compensation for RZ DAC with 50% delay :
- The NTF of the compensated loop-filter exactly matches the actual desired NTF.
- MSA: The ideal modulator is checked with -4.7dB i/p signal for 600,000 clock periods. (no variations on time constant assumed)