Journals

  1. K. M. Vithagan, V. Sundaresha and J. Viraraghavan, "Geometric Programming Approach to Glitch Minimization via Gate Sizing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, doi: 10.1109/TCAD.2022.3207970.
  2. A. F. Davidson and J. Viraraghavan, "Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection," in IEEE Transactions on Education, 2022, doi: 10.1109/TE.2022.3192624.
  3. K. Revanth and V. Janakiraman, "Statistical compact model extraction for skew-normal distributions," in IET Circuits, Devices & Systems, vol. 14, no. 5, pp. 576-585, 8 2020, doi: 10.1049/iet-cds.2019.0366.
  4. Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer 80Kb Logic Embedded High-K Charge Trap Transistor based Multi-Time-Programmable Memory with no Added Process Complexity J. Solid State Circuits,53(3): 949-960 (2018)
  5. Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar Khan, Toshiaki Kirihata, Subramanian S. Iyer: A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. J. Solid-State Circuits 51(1): 230-239 (2016)
  6. Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1920-1924 (2012)
  7. Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1056-1069 (2010)
  8. Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electronics 4(3): 301-319 (2008)

    Conferences

  1. B. Vijayakumar and J. Viraraghavan, "An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401131.
  2. S. A. Balagopal and J. Viraraghavan, "Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180925.
  3. Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer: 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2
  4. Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction for Skewed Gaussian Variations. International Workshop on Physics of Semiconductor Devices 207-209 (December 2013)
  5. Janakiraman Viraraghavan, Shrinivas J. Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach, International Workshop on Physics of Semiconductor Devices, 2011 [Poster]
  6. Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur: Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. VLSI Design 2008: 667-672
  7. Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind: Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. VLSI Design 2008: 685-691

    Patents

  1. Automated Design Rule Checking (DRC) Test Case Generation. US 8,875,064, Oct 28, 2014.
  2. Generic Design Rule Checking (DRC) Test Case Extraction. US 9,292,652, Mar 22 2016.
  3. Dual-bit 3-T high density MTPROM array, US 9659604 B1, May 23, 2017
  4. Disturb-free bitcell and array, US9589658 B1, Mar 7, 2017
  5. Distributed current source/sink using inactive memory elements, US 9721673 B1, Aug 01, 2017
  6. Post-layout thermal-aware integrated circuit performance modeling, US9721059B1, Aug 01, 2017
  7. Test method and structure for integrated circuits before complete metallization, US 20170256468 A1, Jan 02, 2018