team

Deleep R Nair

Professor

Ph.D (EE)  IIT Bombay (2005)

M.Tech (EE)  IIT Bombay (2001)

B.Tech (ECE)   NIT Calicut (1999)

044-2257 4471

deleep@ee.iitm.ac.in

  • Semiconductor Devices - Device Design, Fabrication, Characterization and Numerical modeling.
  • RF MEMS switches and resonators - Design, Fabrication, Characterization and Numerical modeling.

    Current Courses

  • Electric Circuits and Networks (EE2015)
  • VLSI Technology (EE5312)

    Previous Courses

  • Basic Electrical Engineering (EE1100).
  • Electric Circuits and Networks (EE2015).
  • Solid State Devices (EE3001).
  • Professional Ethics (HS3050).
  • VLSI Technology (EE5312).
  • Introduction to Research (EE6021).
  • Advanced CMOS Devices and Technology (EE6346) .
  • Seminar on the History of Electrical Engineering (EE5004) .

Journals

  • RF MEMS capacitive shunt switch for low loss applications K Joy, A Swarnkar, MS Giridhar, A DasGupta, DR Nair Journal of Micromechanics and Microengineering 33 (3), 034004 2023.
  • Scalable Charge-Based Compact Model for Drain Current in Fin-Shaped GaN HEMTs MP Sruthi, A Shanbhag, DR Nair, A Chakravorty, MA Alam, N DasGupta, IEEE Transactions on Electron Devices 70 (3), 979-985 2023.

Conference Proceedings

  • Effect of Undercut due to Isotropic Etch while Releasing on the Performance of TPoS Resonators J Bijay, KNB Narayanan, A Sarkar, A DasGupta, DR Nair, 2023 24th International Conference on Thermal, Mechanical and Multi-Physics 2023
  • Cross-coupled Self-Heating and Consequent Reliability Issues in GaN-Si Hetero-integration: Thermal Keep-Out-Zone Quantified MP Sruthi, MAZ Mamun, DR Nair, A Chakravorty, N DasGupta, 2023 IEEE International Reliability Physics Symposium (IRPS), 1-6 2023.

  • Professor (Nov 2022 - present).
  • Associate Professor (July 2017 - Oct 2022).
  • Assistant Professor (Dec 2011 - June 2017).
  • Senior Engineer - IBM Semiconductor Research and Development Center, Hopewell Junction, NY (April 2005 - October 2011).
  • Device engineer for 65nm, 32nm, 28nm and (early) 14nm CMOS process nodes.
  • Lead device engineer of the multi-company (IBM/Samsung/Infineon/Toshiba/Renesas/GlobalFoundries/ST Microelectronics) 32nm & 28nm bulk CMOS technology development program.

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