Name of the Speaker: Asish Das (EE17S040)
Guide: Dr. Nagendra Krishnapura
Venue/Online meeting link: https://meet.google.com/eaq-hxru-kzu?authuser=0&hs=122
Date/Time: 20th December 2022 (Tuesday), 3:00 PM
To satisfy the ever-increasing need for high data rate over wired channels, multi gigabits per second full-duplex serial links are in huge demand in the industrial and automotive sectors. Whereas 1 Gb/s full-duplex serial links for automotive application are already available in the market, research is going on currently to develop 5 or 10 Gb/s serial links to satisfy customer needs. A major bottleneck in achieving higher data rates is the ADC in the receiver path. Medium resolution ADCs with hundreds of MHz to a few GHz sampling rate is essential for such applications. In this work, our goal is to fulfil the ADC speed requirements while solving the area and power penalties associated with commonly used solutions like flash or pipelined architecture.
The flash topology suffers from the drawback of exponential growth in power and area with the resolution. For a resolution of 6-8 bit, this becomes very prominent. Pipelined ADCs, on the other hand, needs a linear residue amplifier which is power consuming and difficult to design in lower technology nodes. Asynchronous SAR ADCs are very power efficient and can achieve few hundreds of MHz sampling speed for moderate resolution ADCs. We present two high-speed power and area efficient SAR ADC cores which can be used in time-interleaved architectures to achieve sampling speeds in the range of a few GHz. A 6-bit 500-MS/s ADC core is designed for a multi Gb/s ADC application that consumes only 3.08 mW power. Whereas a 200-MS/s 8-bit SAR ADC is designed to be employed in an existing 1-Gb/s serial link application which consumes 2.8 mW power. Both these designs are fabricated in a low-cost 65 nm technology.