Abstract: In recent years, information processing has seen exponential growth due to AI, and data centers are on an ever-increasing trajectory in both scale and capability. A corresponding increase in throughput or bandwidth is required for every data-transfer link or wireline communication link. NRZ modulation schemes and lower technology nodes have pushed the data rates to 10s of Gb/s, but PAM-M (M>2) is embraced to enhance data rates beyond bandwidth limits imposed by CMOS. While PAM-4 has become a standard for 50-100 Gb/s Ethernet, the next generation of links is exploring PAM-8 signaling to achieve 200 Gb/s per lane and beyond. PAM-8 offers a bandwidth-efficient solution by encoding three bits per symbol. However, it introduces severe design challenges, including a drastically reduced vertical eye opening, increased susceptibility to noise and jitter, and the need for precise multi-level clock recovery. This thesis presents a 14 GS/s full-rate digital clock and data recovery (CDR) that recovers a 14 GHz embedded clock and 42 Gb/s data from a PAM-8 modulated bit stream.

In the 42 Gb/s PAM-8 CDR, the received signal is first terminated and buffered to drive a wide-bandwidth track-and-hold circuit at 14 GHz.The sampled signal is fed to a 4-bit charge-based ADC to recover the data bits. Symbol transitions across zero threshold voltage are detected independently on the received signal and combined with deserialized selected data bits to detect the early/late arrival of the sampling clock. The output phase of a 14 GHz I/Q LC-oscillator based phase rotating phase locked loop (PRPLL) serves as the recovered sampling clock phase when digitally controlled by the filtered phase error in a closed loop. ADC’s sampling clock is derived from PRPLL’s four output clock phases using phase interpolators. Designed in TSMC 28nm CMOS and simulated with post-layout parasitics and transient noise, the CDR recovers a 14 GHz clock with 3.4 ps peak-to-peak jitter. The proposed CDR consumes 124 mW from a 0.9 V supply voltage and compares favorably with the state-of-the-art designs.

The CDR loop is designed and fabricated in TSMC 28nm CMOS, and its operation is demonstrated for a 14 GS/s NRZ modulation scheme. Given a PRBS7 NRZ input with 50 mVpk-pk differential amplitude, the CDR recovers a 14 GHz clock. The transmission channel has an estimated loss of 7.1 dB at 7GHz. The recovered clock has 388 fs RMS jitter when integrated from 1 kHz -100 MHz and 4.33 ps peak-to-peak jitter during transient measurements. The CDR observes a sampling time margin of 0.31 UI at BER = 1e-12 and jitter transfer (JTRAN) bandwidth of 1.21 MHz. The proposed CDR dissipates 34.6mW from 0.9 V supply voltage and has the best input sensitivity in power budget compared to the state-of-the-art designs.

Event Details
Title: A 2.95 pJ/b 42Gb/s PAM-8 Clock and Data Recovery in TSMC 28 nm CMOS
Date: May 14, 2026 at 11:00 AM
Venue: Google Meet (http://meet.google.com/aav-bevw-tzy)
Speaker: Mr. Neel Hingrajiya (EE20S075)
Guide: Dr. Saurabh Saxena
Type: MS seminar

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