Prerequisites
Knowledge of Fourier and Laplace transforms, feedback systems, and
CMOS digital gates.
Course contents
This is a self study course. Students are expected to understand
the operation of phase locked loops and delay locked loops, block
level design of the components in them, and their applications such as
frequency synthesizers and clock and data recovery circuits. After
this self study, you should
- know the topologies of frequency synthesizers and clock and data recovery circuits at the block level
- be able to calculate the jitter due to noise from different components.
- be able to model the above in verilogA and simulate them
You can learn about all of these by going through the references
below.
At the end of the semester, you should show simulations of the following
Frequency synthesizer with a multi modulus divider(500MHz output from
a 1MHz reference) Clock and data recovery circuit(500Mb/s input with a
closed eye) using a) Linear phase detector, and b) Bang bang phase
detector
In the final setup, all components other than the VCO can be
macromodels. For the VCO, use a 5 stage ring with 3 inverters loading
each node(0.18um CMOS technology). Use verilogA in Eldo or Spectre for
modeling.
Evaluations
Your grade will be based on the demonstration of the simulation
results and a viva, to be held at the end of the semester.
References
All these references are available from IEEE Explore which can be
accessed through institute proxy 10.65.0.31/32/33.
Overview
- B. Razavi, "Design of monolithic phase locked loops and clock recovery circuits-A tutorial", Monolithic Phase Locked Loops and Clock Recovery Circuits-Theory and Design, IEEE Press, 1996.
- CKK Yang, "Delay locked loops-An overview", Phase Locking in High Performance Systems-From Devices to Architectures, IEEE Press, 2003
Clock generation
- von Kaenel, V. et al., "A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation", IEEE Journal of Solid-State Circuits, Volume 31, Issue 11, Nov. 1996 Page(s):1715 - 1722
- Gutnik V. et al., "Active GHz clock network using distributed
PLLs" IEEE Journal of Solid-State Circuits,
Volume 35, Issue 11, Nov. 2000 Page(s):1553 - 1560
RF frequency synthesizers
- Craninckx, J. and Steyaert, M.S.J., "A fully integrated CMOS
DCS-1800 frequency synthesizer", IEEE Journal of Solid-State
Circuits, Volume 33, Issue 12, Dec. 1998 Page(s):2054 - 2065
- Y Koo et al., "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems" IEEE Journal of Solid-State Circuits,
Volume 37, Issue 5, May 2002 Page(s):536 - 542
- Low-power dividerless frequency synthesis using aperture phase detection
Shahani, A.R.; Shaeffer, D.K.; Mohan, S.S.; Samavati, H.; Rategh, H.R.; del Mar Hershenson, M.; Min Xu; Yue, C.P.; Eddleman, D.J.; Horowitz, M.A.; Lee, T.H.;
Solid-State Circuits, IEEE Journal of
Volume 33, Issue 12, Dec. 1998 Page(s):2232 - 2239
Clock and data recovery
- Clock recovery from random binary signals, JDH Alexander, Electronics Letters, October 1975 (paper, See also page 11-12 of this paper for a brief explanation)
- A self correcting clock recovery circuit, C. R. Hogge, IEEE Journal of Lightwave Technology, December 1985
- A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector
Savoj, J.; Razavi, B.;
Solid-State Circuits, IEEE Journal of
Volume 36, Issue 5, May 2001 Page(s):761 - 768
- A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology
Reinhold, M.; Dorschky, C.; Rose, E.; Pullela, R.; Mayer, P.; Kunz, F.; Baeyens, Y.; Link, T.; Mattia, J.-P.;
Solid-State Circuits, IEEE Journal of
Volume 36, Issue 12, Dec. 2001 Page(s):1937 - 1945
- N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, J. Khoury, K. Lakshmikumar, A. Aggarwal, "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission", IEEE International Solid State Circuits Conference, pp. 60-61,585, Feb. 6-9 2005, San Fransisco, USA.(paper, slides)
Frequency dividers
- A family of low-power truly modular programmable dividers in standard 0.35-¦Ìm CMOS technology
Vaucher, C.S.; Ferencic, I.; Locher, M.; Sedvallson, S.; Voegeli, U.; Wang, Z.;
Solid-State Circuits, IEEE Journal of
Volume 35, Issue 7, July 2000 Page(s):1039 - 1045
- A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-¦Ìm CMOS
Craninckx, J.; Steyaert, M.S.J.;
Solid-State Circuits, IEEE Journal of
Volume 31, Issue 7, July 1996 Page(s):890 - 897
- N. Krishnapura and P. Kinget, "A 5.3 GHz Programmable Divider for
HiPerLAN in 0.25um CMOS", IEEE Journal of Solid State Circuits,
vol. 35, no. 7, pp. 1019-1024, Jul. 2000. (paper slides)
Simulation
Macromodeling can be done using verilogA in Eldo or Cadence/Spectre. For setup
and usage of Eldo, see this
page. Eldo's verilogA documentation can be found at
$anacad/documentation/eldo_vloga.pdf. Cadence's verilogA
documentation can be found at $CDS_INST_DIR/doc/veriaref/veriaref.pdf