• Saurabh Saxena

• ESB 207A

D slot(Mo 11-12; Tu 10-11; We 9-10; Th 12-1)

Registered students can login and see the course page at https://courses.iitm.ac.in/. Resources, tutorials, exam schedules, discussion forum etc. can be accessed from the moodle page.

Login to moodle at https://courses.iitm.ac.in/ to post questions and contact faculty.

• Assignments (10%)
• Quiz-I (25%)
• Quiz-II (25%)
• Project (40%)

The recorded lectures are available here. You can also find lectures from previous years at the same link. The NPTEL online course Analog Circuits also covers a portion of the material.

Assignments will be posted below. You are expected to solve them on your own. You should submit each one by 09:00AM of the due date mentioned. Copying will carry strict penalties.

1. Assignment#1 :Due on 14th Aug. 2017
2. Assignment#2 :Due on 28th Aug. 2017
3. Assignment#3 :Due on 8th Sep. 2017
4. Assignment#4 :Due on 3rd Oct. 2017

Topics include integer/fractional-N phase-locked loops (PLLs), delay-locked loop (DLL), multiplying-DLL, injection-locked PLLs, and sub-sampled PLLs. Building blocks include phase/frequency detectors, charge-pump, LC/ring-oscillators, multi-modulus frequency dividers, active/passive loop-filter, etc.

To develop intuition behind frequency synthesizer design, learning mathematical basis behind operation, and realizing PLLs at architecture and transistor level.

• F. Gardner, Phaselock Techniques, John Wiley & Sons, 2005.
• W. Egan, Phase-Lock Basics, John Wiley & Sons, 2008.
• R. Best, Phase-Locked Loops : Design, Simulation, and Applications, McGraw Hill, 2003.

• Analog Circuits

Attendance will be strictly enforced.