team

Saurabh Saxena

Associate Professor

Ph.D.  (Electrical & Computer Engineering) from University of Illinois at Urbana-Champaign, IL, USA in 2015

B.Tech. & M.Tech.  in Electrical Engineering from IIT Madras, Chennai, India in 2009

044-2257 4457

saurabh.saxena@ee.iitm.ac.in

Personal Link

Room 245A, Electrical Sciences Block, Dept. of Electrical Engineering, IIT Madras, Chennai-600036, Tamil Nadu, India

  • I am an assistant professor in the VLSI group of the department of Electrical Engineering of the Indian Institute of Technology Madras.
  • I graduated with Ph.D. in Electrical & Computer Engineering from University of Illinois at Urbana-Champaign in 2015. At UIUC, I worked with Integrated Circuits and Systems Group under the guidance of Prof. Pavan Kumar Hanumolu. During Ph.D. I focussed on architectural and circuit level techniques for energy efficient high speed serial links.
  • Between 2009 and 2011, I worked as a research assistant under guidance of Prof. Kartikeya Mayaram and Prof. Terri Fiez in the department of Electrical Engineering & Computer Science at Oregon State University. Here I designed high speed discrete-time delta sigma modulators for baseband applications.
  • I graduated with B.Tech. and M.Tech. in Electrical Engineering, under dual degree program in IIT Madras, in 2009.

  • Analog and mixed signal circuits
  • Data converters
  • Serial links
  • Phase-locked loops

  • Naresh Malipeddy Honorable Mention Award for paper titled "A 5-Gb/s PAM4 voltage mode transmitter with current mode continuous time linear equalizer," at IEEE VLSID 2022.
  • 'Early Career Research Award', by Science and Engineering Research Board, Dept. of Science & Technology, GoI, May 2018.
  • ‘Young Faculty Research Fellowship’ under the Visvesvaraya PhD Scheme of the Ministry of Electronics & Information Technology, Govt. of India.
  • New Faculty Seed Grant (NFSG), ICSR, IIT Madras, Jul. 2017.
  • New Faculty Initiative Grant (NFIG), ICSR, IIT Madras, Jul. 2016.

Journals

  • A. K. Bellamkonda, P. H. Rao and S. Saxena, "Intentional Electromagnetic Interference reception in 0.5--2.0 GHz," in IEEE Transactions on Electromagnetic Compatibility, 2022, doi: 10.1109/TEMC.2022.3205160.
  • J. D. Bandarupalli, and S. Saxena, "A 2.5-5.0GHz clock multiplier with 3.2-4.5mUI rms jitter and 0.98-1.06mW/GHz in 65nm CMOS," IEEE Transactions on Circuits and Systems II: Express Briefs.
  • Gautam R and S. Saxena, "A 1.12-1.91 mW/GHz 2.46-4.92 GHz cascaded clock multiplier in 65nm CMOS," IEEE J. Solid-State Circuits, vol. 57, no. 6, pp. 1700-1711, June 2022.
  • S. Mukherjee, A. Das, S. Seth, and S. Saxena, "An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer," IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 67, no. 5, May 2020.
  • J. D. Bandarupalli, G. R, and S. Saxena, "A reconfigurable 0.1-10Gb/s voltage-mode transmitter with 0.2-1V output swing," IEEE Solid-State Circuits Letters, vol. 2, no. 7, pp. 53-56, July 2019.
  • A. Elkholy, S. Saxena, G. Shu, A. Elshazly, and P. K. Hanumolu, “Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1806-1817, June 2018.
  • M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi, and P. K. Hanumolu, “A 5 GHz digital fractional-N PLL using a 1-Bit delta-sigma frequency-to-digital converter in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 9, pp. 2306-2320, Aug. 2017.
  • S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W. -S. Choi, and P. K. Hanumolu,“ A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver,” IEEE J. Solid-State Circuits, vol. 52, no. 5, pp. 1399-1411, May 2017.
  • R. K. Nandwana, S. Saxena, A. Elshazly, K. Mayaram, and P. K. Hanumolu,“A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,” IEEE Trans. Circuits Syst. I, vol. 64, no. 2, pp. 283-295, Feb. 2017.
  • A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1771-1784, Aug. 2016.
  • G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5-Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 428-439, Feb. 2016.
  • T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7Gb/s embedded clock transceiver for energy proportional links,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 3101-3119, Dec. 2015.
  • R. K. Nandwana, T. Anand, S. Saxena, S. –J. Kim, M. Talegaonkar, A. Elkholy, W. –S. Choi, A. Elshazly, and P. K. Hanumolu, “A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method,” IEEE J. Solid-State Circuits, vol. 50, no. 4, April. 2015.
  • S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1827-1836, Aug. 2014.
  • G. Shu, S. Saxena, W. -S. Choi, M. Talegaonkar, A. Elshazly, B. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 1036-1047, April. 2014.
  • R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, “A 75-dB SNDR, 5-MHz bandwidth stage-shared 2-2 MASH DS modulator dissipating 16mW power,” IEEE Trans. Circuits Syst. I. vol. 59, no. 8, pp. 1614-1625, Aug. 2012.
  • S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 12.5-bit 4MHz 13.8mW MASH DS modulator with multirated VCO-based ADC,” IEEE Trans. Circuits Syst. I. vol. 59, no. 8, pp. 1604-1613, Aug. 2012.

Conference Proceedings

  • J. Deepthi, and S. Saxena, "A 0.49-9.8 Gb/S 0.1-1V output swing transmitter with 38.4MHz reference and <30 ns turn-on time," 2023 European Solid-State Device Research & Circuits Conference, 11-14 Sep. 2023. (Accepted)
  • S. Sadhukhan, P. Kumar, A. Bhatia, and S. Saxena, "A class-C injection-locked tripler with 48dB sub-harmonic suppression and 15fs additive RMS jitter in 0.13um BiCMOS process," IEEE International Symposium on Circuits and Systems, May 2022 (accepted).
  • S. Mukherjee, S. Seth and S. Saxena, "A 5-Gb/s PAM4 voltage mode transmitter with current mode continuous time linear equalizer," IEEE VLSID 2022 (Naresh Malipeddy Honorable Mention Award)
  • G. R., J. D. Bandarupalli, S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," IEEE International Symposium on Circuits and Systems, May 2020.
  • S. Mukherjee, A. Das, S. Seth, S. Saxena, "An energy-efficient 3Gb/S PAM4 full-duplex transmitter with 2-tap feed forward equalizer," IEEE International Symposium on Circuits and Systems, May 2020.
  • Q. A. Khan, S. Saxena, and A. Santra, “Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier,” IEEE International Symposium on Circuits and Systems, May 2018.
  • R. K. Nandwana, S. Saxena, A. Elkholy, M. Talegaonkar, J. Zhu, W. S. Choi, A. Elmallah, and P. K. Hanumolu, “A 3-to-10Gb/s 5.75pJ/bit transceiver with flexible clocking in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. 492-493, Feb. 2017.
  • G. Shu, W. S. Choi, S. Saxena, S. -J. Kim, M. Talegaonkar, R. Nandwana, and P. K. Hanumolu, “A 16Mb/s-8Gb/s, 14.1-7.2pJ/bit source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. 398-399, Feb. 2016.
  • A. Elkholy, S. Saxena, and P. K. Hanumolu, “A 4mW wide bandwidth ring-based fractional-N DPLL with 1.9psrms integrated-jitter,” IEEE Custom Int. Circuits Conf., pp. 1-4, Sept. 2015.
  • S. Saxena, G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, “2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” IEEE VLSI Circuits Sym. Tech. Papers, pp. 1-2, June 2015.
  • T. Anand, M. Talegaonkar, A. Elkholy, S. Saxena, A. Elshazly, and P. K. Hanumolu, “A 7Gb/s rapid on/off embedded clock serial link transceiver with 20ns power-on time, 740µW off-state power for energy proportional links in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. 64-66, Feb. 2015.
  • R. K. Nandwana, T. Anand, S. Saxena, S. -J. Kim, M. Talegaonkar, A. Elkholy, W. -S. Choi, A. Elshazly, and P. K. Hanumolu, “A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement,” IEEE VLSI Circuits Sym. Tech. Papers, pp. 1-2, June 2014.
  • M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, S. Saxena, B. Young, W. -S. Choi, and P. K. Hanumolu, “A 4.4-5.4GHz digital fractional-N pll using DSfrequency-to-digital converter,” IEEE VLSI Circuits Sym. Tech. Papers, pp. 1-2, June 2014.
  • A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. K. Hanumolu, “A 20-to-1000MHz 14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. 272-273, Feb. 2014.
  • G. Shu, W. S. Choi, S. Saxena, T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. 150-151, Feb. 2014.
  • S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s 3.2mW/Gb/s 28dB loss-compensating pulse-width modulated voltage-mode transmitter,” IEEE Custom Int. Circuits Conf., pp. 1-4, Sept. 2013.
  • R. K. Nandwana, S. Saxena, and P. K. Hanumolu, “A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC,” IEEE VLSI Circuits Sym. Tech. Papers, pp. 156-157, June 2013.
  • G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu, “A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR,” IEEE VLSI Circuits Sym. Tech. Papers, pp. 278-279, June 2013.
  • R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, “A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH DS modulator dissipating 9mW,” IEEE Custom Int. Circuits Conf., pp. 1-4, Sept. 2011.
  • S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 77dB SNDR, 4MHz MASH DS modulator with a second-stage multi-rate VCO-based quantizer,” IEEE Custom Int. Circuits Conf., pp. 1-4, Sept. 2011.
  • S. Saxena, P. Sankar, and S. Pavan, “Automatic tuning of time constants in single-bit continuous-time delta-sigma modulators,” IEEE International Symposium on Circuits and Systems, pp. 2257-2260, May 2009.

Patents

  • Saurabh Saxena, Gautam R, Jaya Deepthi Bandarupalli, Injection Locked Clock Multiplier with Embedded Phase Interpolator, Indian Patent, 411893, Nov. 2022.
  • Qadeer Khan and Saurabh Saxena, Multi-Phase Low Dropout Voltage Regulator, Indian Patent 383434, Dec. 2021.

Books Authored

  • Book Chapter:
  • S. Saxena and P. K. Hanumolu, “Digital clock and data recovery circuits,” In: Rhee W., editor. Phase-locked frequency generation and clocking, IET Press.
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