team

Janakiraman

Assistant Professor

PhD  Indian Institute of Science Bangalore

M.E.   Indian Institute of Science Bangalore in 2005

B.E  in Electronics and Communication (1999-2003) from Rashtreeya Vidyalaya College of Engineering in Bangalore

044-2257 4485

janakiraman@ee.iitm.ac.in

Personal Link

  • I'm an assistant professor at the Electrical Engineering Department, Indian Institute of Technology Madras. I belong to a very vibrant Integrated Circuits and Systems VLSI group. Watch the short video below to get to know about our group
  • My research focus is primarily on Design Automation techniques for Circuit Design and Low Power Circuit Design for Machine Learning hardware.
  • Since August 2006, Dr. Das has been associated with the Department of Electrical Engineering, IIT Madras, Chennai, India, where he is currently holding a full Professor position. He is also one of the core founding faculty members of the Centre for NEMS and Nanophotonics (CNNP) sponsored by the DeitY, Govt. of India.
  • A number of projects sponsored by DRDO Labs (RCI Hyderabad, IRDE Dehradun), DST and DIT/MeitY have been executed by Dr. Das as a principal investigator. He has published more than 75 research articles in peer reviewed journals and conference proceedings. His present research focus is silicon photonics devices and circuits: optical interconnect and quantum optic application; integrated RF photonics signal processing; lab-on-chip biomedical applications.

  • Low Power Circuit Design Techniques for Machine Learning Hardware.
  • Statistical Analysis in VLSI.
  • Solenoid Control for a Gasoline Pump Injector .
  • I am interested in select Design Automation problems.
  • In particular, problems related to fast monte carlo, Statistical Leakage and Timing analysis.

  • Young Faculty Recognition Award (YFRA) 2019 - IIT Madras

    Previous Courses

  • EE6332 - Modeling and Optimization in VLSI.
  • EE5311 - Digital IC Design.
  • EE6331 - Embedded Memory Deisgn.
  • EE2001 - Digital Systems Lab.
  • EE6361 - Advanced Topics in VLSI.

Journals

  • K M Vithagan, V Sundaresha and J Viraraghavan, Geometric Programming Approach to Glitch Minimization via Gate Sizing, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022.
  • A F Davidson and J Viraraghavan, Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection, in IEEE Transactions on Education, 2022.
  • K Revanth and V Janakiraman, Statistical compact model extraction for skew-normal distributions, in IET Circuits, Devices & Systems, vol 14, no 5, pp 576-585, 8 2020.
  • Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian Iyer 80Kb Logic Embedded High-K Charge Trap Transistor based Multi-Time-Programmable Memory with no Added Process Complexity J Solid State Circuits,53(3): 949-960 (2018).
  • Gregory Fredeman, Donald W Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J Knips, Thomas Miller, Elizabeth L Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar Khan, Toshiaki Kirihata, Subramanian S Iyer: A 14 nm 1-1 Mb Embedded DRAM Macro With 1 ns Access J Solid-State Circuits 51(1): 230-239 (2016).
  • Janakiraman Viraraghavan, Shrinivas J Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach IEEE Trans on CAD of Integrated Circuits and Systems 31(12): 1920-1924 (2012).
  • Janakiraman Viraraghavan, Bharadwaj Amrutur, V Visvanathan: Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks IEEE Trans on CAD of Integrated Circuits and Systems 29(7): 1056-1069 (2010).
  • Janakiraman Viraraghavan, Bharadwaj Amrutur, V Visvanathan: Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks J Low Power Electronics 4(3): 301-319 (2008).

Conference Proceedings

  • B Vijayakumar and J Viraraghavan, An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
  • S A Balagopal and J Viraraghavan, Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study, 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020.
  • Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S Iyer: 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity VLSI Circuits 2016: 1-2.
  • Janakiraman Viraraghavan, Shrinivas J Pandharpure, Josef Watts: Statistical Compact Model Extraction for Skewed Gaussian Variations International Workshop on Physics of Semiconductor Devices 207-209 (December 2013).
  • Janakiraman Viraraghavan, Shrinivas J Pandharpure, Josef Watts: Statistical Compact Model Extraction: A Neural Network Approach, International Workshop on Physics of Semiconductor Devices, 2011 [Poster].
  • Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur: Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization VLSI Design 2008: 667-672.
  • Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H S Jamadagni, N V Arvind: Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations VLSI Design 2008: 685-691.

Patents

  • Automated Design Rule Checking (DRC) Test Case Generation US 8,875,064, Oct 28, 2014.
  • Generic Design Rule Checking (DRC) Test Case Extraction US 9,292,652, Mar 22 2016.
  • Dual-bit 3-T high density MTPROM array, US 9659604 B1, May 23, 2017.
  • Disturb-free bitcell and array, US9589658 B1, Mar 7, 2017.
  • Distributed current source/sink using inactive memory elements, US 9721673 B1, Aug 01, 2017.
  • Post-layout thermal-aware integrated circuit performance modeling, US9721059B1, Aug 01, 2017.
  • Test method and structure for integrated circuits before complete metallization, US 20170256468 A1, Jan 02, 2018.

  • I am interested in music.
  • Mainly Carnatic classcial and Indian Film music.
  • I have also acted in stage plays as part of theatre group Karpanai Kudhirai.
  • My creative efforts in music and theatre bear fruit through this theatre group and Oonjalile Saaindu Kondu is a song whose tune I co-composed with my wife (also sung by her).
  • I am also an avid trekker and have visted the Himalayas thrice looking for that elusive answer to the question "Who am I?"
DEPARTMENT OF Electrical Engineering
Indian Institute of Technology Madras
Chennai, Tamil Nadu, India.
PIN-Code : 600036
Phone: +91-44-2257 4400
Fax: +91-44-22574402
Email:eeoffice@ee.iitm.ac.in
© 2023-All rights reserved.DEPARTMENT OF Electrical Engineering || Website Credits