Electrothermal co-simulation of SOI MOSFET based circuits

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Name of the Speaker: Sonu Kumar (EE19S056)
Guide: Dr. Janakiraman Viraraghavan
Venue/Online meeting link: ESB 210B (Conference Room)
Date/Time: 28th October 2022 (Friday), 2.00 to 3:30 PM

Silicon on Insulator(SOI) has been popular for high-performance designs and is preferred over bulk CMOS technology in certain applications. The presence of buried oxide(BOX) in SOI allows for lower junction capacitance and suppresses the short channel effects making it an attractive option in scaled technologies. However, the lower thermal conductivity of the BOX inhibits heat dissipation to the substrate. This results in heat being confined to the channel region leading to a substantial rise in device temperature, in turn degrading the performance of the device. BSIMSOI models this self-heating using a single-T-node model in SPICE. However, the model assumes that the heat is confined to the same device while in reality, most of the heat flows to the neighbouring devices via metal interconnect. Therefore, it is essential to model the heat exchange between devices at the circuit level.