Events

Electrothermal co-simulation of SOI MOSFET based circuits

  • 28

    Oct

    2022


Name of the Speaker: Sonu Kumar (EE19S056)
Name of the Guide: Dr. Janakiraman Viraraghavan
Link: ESB 210B (Conference Room)
Date/Time: 28th October 2022 (Friday), 2.00 to 3:30 PM

Abstract
Silicon on Insulator(SOI) has been popular for high-performance designs and is preferred over bulk CMOS technology in certain applications. The presence of buried oxide(BOX) in SOI allows for lower junction capacitance and suppresses the short channel effects making it an attractive option in scaled technologies. However, the lower thermal conductivity of the BOX inhibits heat dissipation to the substrate. This results in heat being confined to the channel region leading to a substantial rise in device temperature, in turn degrading the performance of the device. BSIMSOI models this self-heating using a single-T-node model in SPICE. However, the model assumes that the heat is confined to the same device while in reality, most of the heat flows to the neighbouring devices via metal interconnect. Therefore, it is essential to model the heat exchange between devices at the circuit level.

In this work, given a parasitic extracted netlist, a method is proposed to generate a thermal netlist to model the heat exchange between devices via metal interconnect. Previously developed models are physics-based analytical models which involve solving heat equations with appropriate boundary conditions at the interface iteratively. Therefore, solutions for multi-device structures require electrothermal numerical simulations which are time consuming and, hence, not scalable for large circuits. We exploit the Wiedemann Franz Law to convert the parasitic extracted netlist, obtained from the layout of the circuit, into an equivalent thermal netlist, thus eliminating the need for thermal characterization of the interconnect. The generated thermal netlist, along with the electrical netlist, can be co-simulated in SPICE to accurately predict the performance of the circuit. The heat flow via interconnect in a two-device structure using the proposed thermal model has been verified using a physics-based device simulator. A method is devised to co-simulate electrical and thermal netlists for complex digital and analog circuits. Electrothermal circuit simulations show that ignoring heat flow between devices can cause a deviation of up to 35.95% in the gain of an amplifier and a reduction in reference current of up to 17.68% in a reference current generator, which reduces to 5.41% and 7.02% respectively considering heat flow between devices. In general, circuit simulations show that simulating circuits with self-heating while ignoring heat flow between devices leads to a pessimistic design while ignoring the self-heating effect leads to an optimistic design. The proposed methodology enables more realistic designs.