Performance Characterizations and Improvements in Near Memory Processing Architectures

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Name of the Speaker: Mr. Shubhang Pandey ( EE19S057)
Guide: Dr. T G Venkatesh
Venue/Online meeting link: ESB-244 (Seminar Hall)
Date/Time: September 30th (Friday), 11.30 AM to 12.30 PM

Recent advances in 3D fabrication have allowed the development of 3D memory over the logic die. The 3D memory presents itself as a viable solution to the memory wall problem. The 3D memory has stacked DRAM layers connected with Through Silicon Vias (TSVs), responsible for the very high bandwidth. Much effort has been made recently to improve the performance and power of the NMP architectures. Memory Centric Networks (MCNs) are advanced memory architectures that use NMP architectures. MCNs are multiple stacks of 3D memory units equipped with requirement-based processing cores, allowing numerous threads to execute concurrently.