Analysis, design and control of grid-connected inverter with output LCL filter under non-ideal grid conditions

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Name of the Speaker: Mr. Bishal Mondal (EE16D406)
Guide: Dr. Arun Karuppaswamy B
Venue: ESB-244 (Seminar Hall)
Date/Time: 21st December 2022 (Wednesday), 4.15 PM

Grid-tie inverters (GTIs) have a wide range of useful applications. Few examples of GTIs are active front end converter (AFEC), static synchronous compensator (STATCOM), shunt active filter (SAF) and GTI for distributed generation applications (DGAs). The research work spans different aspects of analysis, design and control related to GTIs. An improved phase locked loop (PLL), analysis of converter side inductor ripple current, a new approach to LCL filter design and current controller design are the broad research aspects of this work. In this seminar, the proposed improvements in PLL are discussed.

One of the most important aspects in the control of GTIs is proper synchronization of the converter with the utility grid. The synchronization is usually achieved by phase-locked loops (PLLs). The commonly used PLL structure is the synchronous reference frame based PLL (SRF-PLL) which is implemented in rotating direct-quadrature axis (dq axis). Under non-ideal grid voltage conditions, the fundamental positive-sequence voltage of the utility appears as a dc component in the dq frame while the abnormalities like harmonics, unbalance and dc-offset appear as ac components. The fundamental positive-sequence voltage is the information of interest for synchronization and controls and is to be separated.