Name of the Speaker: Mr. Seshadri G (EE16D005)
Guide: Dr. Krishna Vasudevan
Venue/Online meeting link: https://iitmadras.webex.com/iitmadras/j.php?MTID=m34c839ba9d0b54cbdc4acd35687d0147
Date/Time: 17th December 2022 (Saturday), 10.00 AM
A considerable level of even ordered harmonics are observed in the grid voltage measured at different industrial sites. These even ordered harmonics create triple the grid frequency component in the DC side of Adjustable Speed Drives (ASDs). Due to this, a 150 Hz current component is created in the electrolytic capacitors of ASDs and considerably impacts the heating in the capacitor. Also, Total Harmonic Distortion (THDi) of the current drawn by the ASD is adversely affected due to the even ordered harmonics. To address this problem, a cost-effective approach based on suitable triggering of the SCRs in the bridge of ASD is proposed. This approach may suppress the effect of even ordered harmonics on capacitor ripple current and improve the source current THDi. The proposed strategy is analyzed by simulations under different grid impedance and harmonic combination cases, and validated by a hardware test setup.