Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis

Abstract: Phase-locked loops(PLL) are designed with a low bandwidth to attenuate reference phase noise and spurs. The disadvantage of having a low bandwidth is the increased settling time. A technique for improving the settling time of an integer-N PLL by dynamically varying the division modulus is presented. This is achieved by passing the frequency step control signal through a suitable pre-emphasis filter before applying it to the multi-modulus divider. Noise performance and stability remain unaffected since the loop gain is not altered. No changes to the analog portion of the PLL are required. Simulation of a third-order 1-GHz PLL with 10-MHz reference and 500-kHz bandwidth shows a 57% reduction in the settling time. The settling time reduces by 45–75% for ±20% variation in the component values.

Event Details
Title: Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis
Date: April 02, 2026 at 09:00 AM
Venue: Google Meet (https://meet.google.com/goe-sfne-dum)
Speaker: Mr. Sumit Kumar (EE10D047)
Guide: Dr. Nagendra Krishnapura
Type: PHD seminar