Abstract: Modern power applications such as electric vehicles, renewable energy, and industrial systems require devices with high efficiency, power density, thermal robustness, and short-circuit capability. However, the inherent material limitations of silicon—its low critical electric field and narrow bandgap—restrict high-voltage and high-temperature performance. Although SiC offers superior properties, its poor short-circuit withstand time, tSC remains a critical limitation for reliable operation.

This research addresses key challenges in SiC VD-MOSFET design, focusing on improving breakdown voltage, VBR, specific on-resistance, Ronsp, and short-circuit reliability. First, an optimized drift-layer design methodology is proposed, which relaxes the conventional emphasis on minimizing drift resistance. By allowing a slightly higher drift resistance, the approach enables improved doping and thickness selection, achieving up to 14% higher VBR and 18% improvement in tSC with negligible Ronsp penalty.

Second, a novel p+ implant near the p-base corner is introduced to enhance short-circuit performance. This modification reduces peak short-circuit current and slows thermal runaway, significantly extending tSC. Simulation results show an increase in tSC from 2.74 μs to 19 μs for a 0.6 kV device, with only a 12% increase in Ronsp. The design remains compatible with existing gate driver technologies used in Si IGBT based converters.

Finally, to address fabrication non-idealities affecting breakdown voltage, an improved floating field ring (FFR) design is developed. A Mirrored Floating Field Ring, MFFR, structure is also proposed, which significantly reduces VBR degradation under lithographic and interface charge variations—from 48% to 16%—thereby enhancing device robustness and enabling reduced Ronsp.

Overall, the proposed techniques provide a comprehensive pathway to improve the performance and reliability of SiC VD-MOSFETs for advanced power applications.

Event Details
Title: Design of SiC MOSFET to Improve Short Circuit and Blocking Performance (PhD Viva Voce)
Date: April 21, 2026 at 2:00 PM
Venue: Google Meet (https://meet.google.com/fde-owzg-hma)
Speaker: Mr. Prashant Singh (EE18D026)
Guide: Dr. Karmalkar S
Type: PHD seminar

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