E4332: VLSI Design Laboratory, Spring 2005
Layout and verification in AMI 0.5μm process

• Initial setup
• Layout
  • Design rules
  • Components
  • Creating pins
  • Guidelines
• Padframe
• Design rule checking
• Layout versus Schematic
• Post layout simulation

Initial setup

On starting Cadence, type the following in the CIW
load("/usr/tech/ami050/cdsinit") This sets up the layer map so that you can see the layouts correctly.

Your cds.lib should include the following lines

INCLUDE /usr/tools/cds/setup/cds.lib
DEFINE ami050 /usr/tech/ami050/cdslib/ami050
DEFINE ami_pads /usr/tech/ami050/cdslib/ami_pads
DEFINE ami_example /usr/tech/ami050/cdslib/ami_example

Layout

Go to Options -> Display and set both the X Snap Spacing and Y Snap Spacing to 0.05. This is to ensure that there will be no off-grid errors.

Design rules

The design rule manual can be found at /usr/tech/ami050/ami500hakx/Rev6.7/design_rules/C5X_4500099_RevR.pdf on the teaching lab computers. Some key rules are explained below.

• Transistors: The minimum drawn length of the transistor is 0.6μm, not 0.5μm. It reduces to an effective length of 0.5μm during fabrication. Therefore, please use 0.6μm for the minimum length.
• NWELL: pMOS transistors should be enclosed in an NWELL layer. The design rules require that there be another layer NFIELD coincident with the NWELL. So draw the NWELL wherever necessary, and add a coincident NFIELD layer.
• Contacts: contacts can be accessed via the bindkey 'o'. Use NDIFCT(N-well contacts), PDIFCT(substrate contacts), M1POLY(metal1-poly), VIA(metal2-metal1), and VIA2(metal3-metal2). Ignore the other contacts that pop up.

Basic design rule summary

• Transistor dimensions: minimum length=0.6μm ; minimum width=1.1μm
• All contact sizes(exact): 0.5μm x 0.5μm
• M1, M2, M3 width:
• M1, M2, M3 spacing:
• Wide M1, M2, M3 spacing:

The Layer selection window shows a large number of layers. You should not have to use more than the first twenty or so in your design.

Components

Cell Standard_examples in library ami_example has examples of resistors, MOS transistors, and bipolar transistors.

• Transistors: Instantiate layout views of nmos or pmos cells in the library ami050. You can enter the length l total width w and the number of fingers nf. The resulting layout will have nf fingers of width w/nf which you then have to connect in parallel. I suggest retaining the multiplier m at 1.
• Resistors: The high resistivity ones (1kΩ per square) are formed by a line of POLY2 covered with HIRES layer to prevent it from being doped to a high resistance. At this point, there is no component that you instantiate. Just draw a POLY2 line and a HIRES box enclosing it. For LVS purposes, also draw a rectangle on RES layer over the polysilicon segment that is intended to be used as the resistor. The LVS tool does identify this as a resistor. So you will be able to run LVS on the whole schematic. Since there is no corresponding symbol(the component in the schematic view is an ideal resistor from analogLib), there will be LVS error, but you should only have instance errors. If you look at the Layout netlist from the LVS window, you'll be able to see the length and width of the resistors. You need to make sure that these are what you want.
• Capacitors: This is formed between POLY1 and POLY2 layers. At this point, there is no corresponding component in the schematic. Just draw POLY1 and POLY2 layers on top of each other. For LVS purposes, draw CAPM layer over the POLY1-POLY2 overlapping area(parallel plate capacitor area). The LVS tool does identify this as a capacitor. So you will be able to run LVS on the whole schematic. Since there is no corresponding symbol(the component in the schematic view is an ideal capacitor from analogLib), there will be LVS error, but you should only have instance errors. If you look at the Layout netlist from the LVS window, you'll be able to see the area of the capacitor. You need to make sure that the area is the value that you want.

Creating pins

To label a net(say on Metal1), create a label(bindkey = 'l') in Metal1 drawing layer and place it on the net.

The rules file doesn't seem to recognize symbolic pins or shape pins(The ones created using 'Control-p'). Let me know if you find otherwise

Layout guidelines

These are suggestions, not hard and fast rules

• Flow of layout: In general, circuits consist of a cascade of blocks with common Vdd and Gnd. Having the layout look like the schematic, i.e. Vdd rail on top, Gnd on the bottom, signal flowing from left to right usually works well.

• Interconnects: Usually it works well to use 2 metal layers in the sub blocks, one each for horizontal and vertical directions and to use the third metal layer for higher level connections.

  The width of metal interconnect layers is determined by the current that is supposed to flow in them. There are two constraints

  1. Electromigration: This is the maximum current that can flow through a given width of metal line. In the current process, this is about 1mA/μm. The lines driving the LED display in the digital clock, for example, need to be sufficiently wide.
  2. Resistive voltage drop along the line: The metal interconnects have a non zero resistance, and consequently, voltage drops across them. This voltage drop must be negligible. The absolute drop that can be tolerated depends on the context. This is likely to be of concern in particularly long lines, power supply lines etc. The power supply lines in the AM radio, for example, should not have a voltage drop exceeding about 25mV with a 5V supply. Larger drops can be tolerated in digital circuits.
  Related to this is the number of contacts you need to use. Try not to use solitary contacts. Use at least 2. The electromigration limit for contacts is about 1mA/contact.
• Substrate and n-well connections: You need to have substrate and n-well contacts so that the body of MOS transistors is connected to a known voltage. These contacts need to be "sufficiently" close to the transistors. For digital circuits, body terminals of nMOS and pMOS transistors are connected to Gnd and Vdd respectively. Having substrate/well contacts along the Vdd lines should be sufficient. For analog circuits, where transistors tend to be larger, it is a good idea to have substrate/well contacts around(say, on 3 sides) transistors of each stage(e.g. each amplifier stage in the radio).
• Sensitive analog circuits need to be laid out carefully. Especially a high gain amplifier such as the one present in the radio can oscillate in presence of small amounts of unwanted feedback. Avoid crossings of signal and bias lines or crossings of output and input signals of a high gain amplifier.

Pads and Padframe

The pads are in the library ami_pads. The pads which you will be using are listed below. The pads have associated schematics which you can plop into the schematic for LVS and simulations. Connections to all pads from the circuit are in Metal2.

1. PadARef: Pad with ESD. General purpose pad. Use this for all analog signals and digital outputs.
2. PadIO: Pad with ESD and series resistor: Use this for digital inputs that are going to MOS gates. Don't use this pad for any input that has dc flowing through it.
3. PadGnd: For ground supply
4. PadVdd: For power supply
5. PadSpace: To fill up the spaces between pads.

Design rule checking

In your home directory, create a file called assura_tech.lib with the following line in it
DEFINE AMI050 /usr/tech/ami050/ami500hakx/Rev6.7/assura3

From the layout window, select 'Assura -> Run DRC'. In the form, select AMI050 for the technology. The correct rules files should then be selected and you should be able to run DRC.

Layout versus Schematic

In your home directory, create a file called assura_tech.lib with the following line in it
DEFINE AMI050 /usr/tech/ami050/ami500hakx/Rev6.7/assura3

From the layout window, select 'Assura -> Run LVS'. In the form select AMI050 for the technology. The correct rules files should then be selected and you should be able to run LVS.

Post layout simulation