| Both sides previous revision
Previous revision
Next revision
|
|
start [2017/03/23 12:22] nagendra |
|
|
|
start [2014/05/27 08:08] (current) nagendra |
|
| ====== Integrated Circuits and Systems group, IIT Madras ====== |
|
| Welcome to the homepage of the Integrated Circuits and Systems group in the [[http://www.ee.iitm.ac.in/|Department of Electrical Engineering]] at [[http://www.iitm.ac.in/|IIT Madras]]. We are located in a beautiful wooded campus in southern Chennai. |
|
| Our [[people/start|faculty]] and students are involved in research in the areas of analog, mixed signal, and RF design, analysis and simulation of noise in circuits, VLSI DSP architectures, and reconfigurable computing. Click on the tabs above to find out more about us and our research. |
|
| We regularly have openings for students in our research group. If you wish to study here, go through [[forstudents/start|this page]] for more information and contact the [[people/start|faculty member]] working in your area of interest. Here is a short video about our group: |
|
|
<html><iframe width="560" height="315" src=== 2017 Texas Instruments Research Associateships for MS by research at IIT Madras ===== |
* Applications to the [[http"https://www.eeyoutube.iitm.ac.incom/vlsiembed/tiiprogram/start|Texas Instruments research associateship program]] leading to an MS degree at IIT Madras will open between 27th March and 7th April 2017. Information about this program can be found at [[http://www.ee.iitm.ac.in/vlsi/tiiprogram/start|this link]]. |
|
wAZWBAM6-Ts" frameborder===== Upcoming GIAN courses ===== |
The following course will be offered at IIT Madras as a part of the [[http:"0" allowfullscreen></iframe></www.gian.iitkgp.ac.in/|Global Initiative of Academic Networks(GIAN)]]. To register, visit [[http://www.gian.iitkgp.ac.in/]]. |
|
* [[http://www.gian.iitkgp.ac.in//files/brochures/BR1474256000GIAN_Brochure_Integrated_Phase_and_Frequency_Synthesis_Shanthi_Pavan_EE_1_to_15_March_2017.pdf|Integrated Phase and Frequency Synthesis]] by Sudhakar Pamarti(University of California at Los Angeles, USA), 1st to 15th March 2017.html> |
|
| ===== News ===== |
* Anoop Narayan Bhat received the [[http://www.iesaonline.org/Technovation2016/index.html|2016 Technoinventor award]] in the masters category from the [[http://www.iesaonline.org/|India Electronics and Semiconductor Association]] at their [[http://iesaonline.org/vs2017/index.html|2017 vision summit]]. |
* The paper **Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM** by Sumit Devandla Sekhar, Kanhaiya Kumarand Nagendra Krishnapura will be presented at the 2017 International Symposium on circuits and Systems to be held in Baltimore, USA in May 2017. |
* The paper **On Linear Periodically Time Varying (LPTV) Systems with Modulated InputsM Praneeth, and Their Application to Smoothing Filters** by Shanthi Pavan will be presented at the 2017 International Symposium on circuits and Systems to be held in BaltimoreNidhin S Thiyagaraj, USA in May 2017. |
|
{{:uds_2ndedition.jpg?direct&480|Order it on Amazon}} |
|
**Understanding Delta-Sigma Data Converters** // Second Edition// \\ Shanthi PavanPranav Chaitanya, Regin Jesudason G, Shailender Singh, Richard Schreier and Gabor Temes \\ Wiley and IEEE Press Series on Microelectronic Systems \\ |
[[http://wwwSrikrishnan R have joined our group. amazon.com/Understanding-Delta-Sigma-Converters-Microelectronic-Systems/dp/1119258278|Now available! Order it on Amazon]] |
|
* The paper **A 500Mb/s, 200pJ/bit die-warm welcome to -die bidirectional link with 24kV surge isolation and 50kV/s CMR using resonant inductive coupling in 180nm CMOS** by Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura will be presented at the 2017 International Solid-State Circuits Conference to be held in San Francisco, USA in Feball of them. 2017. |
* The paper **A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset** by Ashwin Kumar R. S., Debasish Behera, and Nagendra Krishnapura was presented at the 2017 VLSI Design Conference held in Hyderabad in Jan. 2017. |
|
| ([[newsarchives|Archive]]) |