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start [2017/08/28 21:39] nagendra |
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start [2025/10/18 10:16] (current) nagendra |
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| Our [[people/start|faculty]] and students are involved in research in the areas of analog, mixed signal, and RF design, analysis and simulation of noise in circuits, VLSI DSP architectures, and reconfigurable computing. Click on the tabs above to find out more about us and our research. |
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We regularly have openings for students in our research group. If you wish ===== Applications to study here, go through [[forstudents2026 January PhD/start|this page]] for more information and contact the [[people/start|faculty member]] working in your area of interest. Here is a short video about our group:MS interviews ===== |
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<html><center><iframe width="560" height="315" src="Applications to the regular PhD/MS programs are now open. The deadline is **31 October 2025**. See links below for more information. |
* https://wwwresearch.youtubeiitm.comac.in/ embed/wAZWBAM6-Ts" frameborder="0" allowfullscreen></iframe></center></html>: Applicants to all programs must fill out the application form here |
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===== MSWe regularly have openings for students in our research group. If you wish to study here, go through [[forstudents/PhD at IIT Madras start|this page]] for more information and GATE 2018 =====contact the [[people/start|faculty member]] working in your area of interest. Here is a short video about our group: |
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A number of MS/PhD positions are available in our group. Bachelors students applying for MS or (direct) PhD require a GATE score. Students who intend to apply to these positions, including those in the final year of their bachelors' program, are urged to register for [[http<html><iframe width="560" height="315" src="https://www.gateyoutube.iitg.ac.incom/|GATE 2018]] in ECembed/EE/IN. For these research positions, selections are through a test and interview and GATE score is used only for shortlisting for the test and interview. GATE requirement is waived for MS and direct PhD applicants from IITs with CGPA >wAZWBAM6-Ts" frameborder=8."0. GATE requirement is waived for direct PhD applicants from CFTIs with CGPA " allowfullscreen>8.0. See [[http:</iframe></www.ee.iitm.ac.in/2017/03/m-s-ph-d-admission-criteria-july-nov-2017/|this link]] and [[http://www.ee.iitm.ac.in/vlsi/tiiprogram/start|this link]] for detailed shortlisting criteria used this year. html> |
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| ===== News ===== |
* AsishDevandla Sekhar, AshutoshKanhaiya Kumar, ChintanM Praneeth, GauthamNidhin S Thiyagaraj, IrabanPranav Chaitanya, KishoreRegin Jesudason G, RaghavendraShailender Singh, and Venkata Sesha Rao Srikrishnan R have joined the ICS our group. A warm welcome to all of them. |
* Online courses [[https://onlinecourses.nptel.ac.in/noc17_ee13/preview|Basic Electrical Circuits]] and [[https://onlinecourses.nptel.ac.in/noc17_ee14/preview|Analog circuits]] will be run on NPTEL starting 24th July 2017. Click on the respective links to register. Registration deadline is 24th July. |
* Our recorded lectures will now become available on our [[https://www.youtube.com/channel/UCePMtM40OBXEwoA8aFwkFxg/playlists|YouTube channel]]. They will continue to be available at [[http://www.ee.iitm.ac.in/videolectures|http://www.ee.iitm.ac.in/videolectures]]. |
* Anoop Narayan Bhat received the [[http://www.iesaonline.org/Technovation2016/index.html|2016 Technoinventor award]] in the masters category from the [[http://www.iesaonline.org/|India Electronics and Semiconductor Association]] at their [[http://iesaonline.org/vs2017/index.html|2017 vision summit]]. |
* The paper **Optimum Scaling of Stages in a Frequency Divider Chain for Best Jitter FoM** by Sumit Kumar and Nagendra Krishnapura will be presented at the 2017 International Symposium on circuits and Systems to be held in Baltimore, USA in May 2017. |
* The paper **On Linear Periodically Time Varying (LPTV) Systems with Modulated Inputs, and Their Application to Smoothing Filters** by Shanthi Pavan will be presented at the 2017 International Symposium on circuits and Systems to be held in Baltimore, USA in May 2017. |
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{{:uds_2ndedition.jpg?direct&480|Order it on Amazon}} |
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**Understanding Delta-Sigma Data Converters** // Second Edition// \\ Shanthi Pavan, Richard Schreier and Gabor Temes \\ Wiley and IEEE Press Series on Microelectronic Systems \\ |
[[http://www.amazon.com/Understanding-Delta-Sigma-Converters-Microelectronic-Systems/dp/1119258278|Now available! Order it on Amazon]] |
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* The paper **A 500Mb/s, 200pJ/bit die-to-die bidirectional link with 24kV surge isolation and 50kV/s CMR using resonant inductive coupling in 180nm CMOS** by Subhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Jhankar Malakar, and Nagendra Krishnapura will be presented at the 2017 International Solid-State Circuits Conference to be held in San Francisco, USA in Feb. 2017. |
* The paper **A Low Power Multi-Channel Input Delta-Sigma ADC Without Reset** by Ashwin Kumar R. S., Debasish Behera, and Nagendra Krishnapura was presented at the 2017 VLSI Design Conference held in Hyderabad in Jan. 2017. |
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