This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
|
publications:start [2022/08/23 14:56] nitin [2020] |
publications:start [2024/12/28 03:09] (current) nagendra |
||
|---|---|---|---|
| Line 1: | Line 1: | ||
| ====== Publications ====== | ====== Publications ====== | ||
| + | ===== 2024 ===== | ||
| + | * C. Bheemisetti et al. "A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver." IEEE Journal of Solid-State Circuits, [[https://ieeexplore.ieee.org/document/10723273|doi: 10.1109/JSSC.2024.3449115]]. | ||
| + | * Aswani Kumar Unnam, P. Banerjee and N. Krishnapura, "An 81.5dB SNDR, 2.5 MHz Bandwidth Incremental Continuous-Time Delta-Sigma ADC in 180 nm CMOS," IEEE Solid-State Circuits Letters, vol. 7, pp. 191-194, 2024. [[https://ieeexplore.ieee.org/abstract/document/10552799|doi: 10.1109/LSSC.2024.3412634]]. | ||
| + | * A. Narayanan, A. Bhat and N. Krishnapura, "A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays," IEEE Journal of Solid-State Circuits, vol. 59, no. 9, pp. 2818-2830, Sept. 2024. [[https://ieeexplore.ieee.org/document/10471881|doi: 10.1109/JSSC.2024.3373620.]] | ||
| + | ===== 2023 ===== | ||
| + | * P. Kumar and N. Krishnapura, "Signal-Strength Detector Based on CMOS-Inverter Supply Current," //IEEE Solid-State Circuits Letters//, [[https://ieeexplore.ieee.org/document/10226425|doi: 10.1109/LSSC.2023.3307361]]. | ||
| + | * Subha Sarkar, Rajat Agarwal, Nagendra Krishnapura, "Bandpass filter and oscillator ICs with THD < -140dBc at 10Vppd for testing high-resolution ADCs," //2023 International Solid-State Circuits Conference//, San Francisco, USA, Feb. 2023. Accepted for presentation. [[https://ieeexplore.ieee.org/document/10067771|doi: 10.1109/ISSCC42615.2023.10067771]]. | ||
| + | * S. Ramprasath, M. Madhusudan et al., "A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts," //ACM Transactions on Design Automation of Electronic Systems//, [[https://dl.acm.org/doi/10.1145/3580477|doi: 10.1145/3580477]]. | ||
| + | * J. Poojary, S. Ramprasath et al., "Exploration of Design / Layout Tradeoffs for RF Circuits using ALIGN," // IEEE Radio Frequency Integrated Circuits Symposium (RFIC)//, San Diego, USA, June 2023. [[https://doi.org/10.1109/RFIC54547.2023.10186141|doi: 10.1109/RFIC54547.2023.10186141]]. | ||
| + | |||
| + | ===== 2022 ===== | ||
| + | * R. S. A. Kumar, N. Krishnapura and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," //IEEE Journal of Solid-State Circuits//, vol. 57, no. 11, pp. 3384-3395, Nov. 2022, [[https://ieeexplore.ieee.org/document/9777856|doi: 10.1109/JSSC.2022.3171790.]] | ||
| + | * K. M. Vithagan, V. Sundaresha and J. Viraraghavan, "Geometric Programming Approach to Glitch Minimization via Gate Sizing," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, doi: 10.1109/TCAD.2022.3207970. | ||
| + | * A. F. Davidson and J. Viraraghavan, "Layout-Based Digital IC Course Projects in Large Classes: Implementation, Evaluation, and Plagiarism Detection," in IEEE Transactions on Education, 2022, doi: 10.1109/TE.2022.3192624. | ||
| + | * S. Ramprasath, M. Madhusudan et al., "Analog/Mixed-Signal Layout Optimization using Optimal Well Taps," //International Symposium on Physical Design//, Virtual Event Canada, Apr. 2022. [[https://dl.acm.org/doi/10.1145/3505170.3506728|doi: 10.1145/3505170.3506728]] | ||
| + | * T. Dhar, S. Ramprasath et al., "A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement," //Design, Automation & Test in Europe Conference & Exhibition (DATE)//, Antwerp, Belgium, Mar. 2022. [[https://doi.org/10.23919/DATE54114.2022.9774621|doi: 10.23919/DATE54114.2022.9774621]] | ||
| + | |||
| ===== 2021 ===== | ===== 2021 ===== | ||
| * R. S. A. Kumar, N. Krishnapura and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," //IEEE Journal of Solid-State Circuits//. Early access. | * R. S. A. Kumar, N. Krishnapura and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," //IEEE Journal of Solid-State Circuits//. Early access. | ||
| Line 15: | Line 32: | ||
| * S. Guddanti and Q. A. Khan, "A High Efficiency Fast Transient Zero Output Ripple Buck Converter Using Split PWM Controller with Inductor Mismatch Compensation," //2021 IEEE International Symposium on Circuits and Systems (ISCAS)//, 2021. | * S. Guddanti and Q. A. Khan, "A High Efficiency Fast Transient Zero Output Ripple Buck Converter Using Split PWM Controller with Inductor Mismatch Compensation," //2021 IEEE International Symposium on Circuits and Systems (ISCAS)//, 2021. | ||
| * A. Chitnis, R. Chauhan, D. Kaur and Q. Khan, "A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT," //2021 IEEE Custom Integrated Circuits Conference (CICC)//, 2021. | * A. Chitnis, R. Chauhan, D. Kaur and Q. Khan, "A 0.75-5V, 15.8 nA with 1.8 μs Delay Supply Voltage Supervisor using Adaptively Biased Comparator and Sample & Hold Technique for IoT," //2021 IEEE Custom Integrated Circuits Conference (CICC)//, 2021. | ||
| + | * A. Nallathambi, S. Sen, A. Raghunathan, N. Chandrachoodan, “Probabilistic spike propagation for efficient hardware implementation of spiking neural networks”, Frontiers in Neuroscience, vol 15, 2021 | ||
| + | * B. N. G. Koneru, N. Chandrachoodan and V. Vasudevan, "A Smoothed LASSO-Based DNN Sparsification Technique," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 10, pp. 4287-4298, Oct. 2021 | ||
| + | * B. Vijayakumar and J. Viraraghavan, "An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401131. (Accepted for poster) | ||
| ===== 2020 ===== | ===== 2020 ===== | ||
| Line 29: | Line 49: | ||
| * A. D. Carmine, A. Santra, Q. Khan, "A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | * A. D. Carmine, A. Santra, Q. Khan, "A current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | ||
| * K. Peetala, A. Ranjan, R. Aenkamreddi, Q. Khan, "An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | * K. Peetala, A. Ranjan, R. Aenkamreddi, Q. Khan, "An Area Efficient, High-Resolution Fully Foldable Switched-Capacitor DC-DC Converter with 16% Efficiency Improvement," //2020 International Symposium on Circuits and Systems (ISCAS)//, 17-20 May 2020, Seville, Spain. (Accepted for poster presentation). | ||
| + | * S. A. Balagopal and J. Viraraghavan, "Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180925. (Accepted for poster) | ||
| * M. V. Praveen and N. Krishnapura, "High Linearity Transmit Power Mixers Using Baseband Current Feedback," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://ieeexplore.ieee.org/document/8889460|doi: 10.1109/JSSC.2019.2945962]] | * M. V. Praveen and N. Krishnapura, "High Linearity Transmit Power Mixers Using Baseband Current Feedback," //IEEE Journal of Solid-State Circuits//, vol. 55, no. 2, pp. 272-281, Feb. 2020. [[https://ieeexplore.ieee.org/document/8889460|doi: 10.1109/JSSC.2019.2945962]] | ||
| * A.Baluni and S.Pavan, "A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and >100 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC," // IEEE Custom Integrated Circuits Conference (CICC)//, March 2020. **(Outstanding Student Paper Award)** | * A.Baluni and S.Pavan, "A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and >100 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC," // IEEE Custom Integrated Circuits Conference (CICC)//, March 2020. **(Outstanding Student Paper Award)** | ||
| Line 431: | Line 452: | ||
| ====== Patents ====== | ====== Patents ====== | ||
| + | * P. Yadav and S. Ramprasath, " Keep-through regions for handling end-of-line rules in routing," US 11,586,796 B1, Feb. 21, 2023. [[https://patents.google.com/patent/US11586796B1|US11586796B1]] | ||
| * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, "Current measurments in switching regulators", US 9,755,518, September 5, 2017. [[https://patents.google.com/patent/US9755518|US9755518B2]] | * M. Bansal, M. McGowan, I. Mirea, Q. Khan, T. Stockstad, B. Walker and T. Sutton, "Current measurments in switching regulators", US 9,755,518, September 5, 2017. [[https://patents.google.com/patent/US9755518|US9755518B2]] | ||
| * M. Bansal, Q. Khan and C. Shi, "Average current mode control of multi-phase switching power converters," US 9,442,140, Sep. 13, 2016. [[https://patents.google.com/patent/JP6185194B2/en|JP6185194B2]] | * M. Bansal, Q. Khan and C. Shi, "Average current mode control of multi-phase switching power converters," US 9,442,140, Sep. 13, 2016. [[https://patents.google.com/patent/JP6185194B2/en|JP6185194B2]] | ||