http://www.ee.iitm.ac.in/vlsi/ 2026-04-04T08:58:08+00:00 http://www.ee.iitm.ac.in/vlsi/ http://www.ee.iitm.ac.in/vlsi/lib/tpl/zenlike/images/favicon.ico text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p1?rev=1293186919&do=diff Development of the state of the art VLSI design facility The objective of the project was to improve the infrastructure available in VLSI design area and bring it to the state-of-the art level so that * new theoretical and practical courses in VLSI design could be introduced in the curriculum for the purpose of manpower development. * specific projects can be taken up in VLSI design for building up expertise so that we would keep up the tempo and be collateral with the state-of-the-art … text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p2?rev=1293186919&do=diff Design of Analog and Mixed mode ASICs and Development of Analog ASIC Design Tools The aim of the project was to develop expertise in the design of analog and mixed mode ASICs especially. Design of a voltage reference circuit with 10 PPM temperature coefficient was done and the fabrication was successfully carried out in coordination with BEL, Bangalore. In addition, an analog array was also designed and fabricated. Various test structures were designed for extracting Gummal-Pool parameters as… text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p3?rev=1293186919&do=diff Feasibility Studies on Design and Implementation of Basic DSP Building Blocks The project aimed at conducting studies to establish the viability of designing and implementing circuit blocks that form part of a Digital Signal Processor (DSP). A Multiplier-Accumulator (MAC) module was taken up as the best example for providing us with the necessary insight into the design and implementation of such blocks. text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p4?rev=1293186919&do=diff Study of Neural Network Based Coding Schemes for Telemetry Data This project evaluated the performance of various coding schemes used for compression of multiple channel telemetry data. Lossless transmission and latency have been important considerations in addition to the compression ratio. Several schemes including linear predictive coding and entropy coding schemes such as adaptive Huffman coding and adaptive arithmeitc coding were studied and their performance compared with non-linear predi… text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p5?rev=1293186919&do=diff Special Manpower Development for VLSI Design and related Software This is an on-going project with participation by a number of Institutions. IIT Madras is identified by DOE as one of the seven Resource Centres (RCs) mainly responsible for carrying out the project. The RCs are expected to develop learning material that would conform to B.Tech/M.Tech curriculum in the relevant field and help other educational institutions with these learning materials. In addition, faculty from other institution… text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p6?rev=1293186919&do=diff Design and Implementation of a Multi - FPGA Reconfigurable Processor for Image Compression Applications. A dynamically reconfigurable video encoder to switch among many different applications is designed. The scheme is suitable for FPGA implementation and conforms to JPEG, MPEG-1, MPEG-2, and H.263 standards. The scheme has emerged as an efficient and cost-effective solution for video compression as a result of innovative design using well-partitioned algorithms, highly pipelined architecture a… text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p7?rev=1293186919&do=diff Development of HDL Cores for FPGA implementation of Demodulator for Satellite data. Reception of voice and image data over satellite requires bandwidths of 64 Kbps or more. Existing scheme for demodulation uses an advanced DSP with a maximum bit rate of 64 Kbps. In order to increase the bandwidth capability, modification of the present scheme using a combination of ADSP and FPGA has been undertaken. The work involves development of a new algorithm and its software implementation for validatio… text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p8?rev=1293186919&do=diff Modern design aids for electronic circuits and systems Traditional method for designing analog and digital systems is to use electronic equipments and kits, tailor-made for each specific application. This approach requires large working space and results in increase of inventory over the years. In the long run, the cost of equipping and upgrading the laboratory becomes quite expensive. However, with the availability of Personal Computers and design software at affordable prices, experiments are… text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p9?rev=1293186919&do=diff Development of Synthesizable VHDL Cores for DSP Although digital signal processors (DSPs) are suitable for filters and multiply and accumulate (MAC) intensive operations, they are not suitable for video processing applications, since they have limited pipelining and parallelism inherent in their architecture. On the other hand, FPGA/ASIC implementations exploit massively parallel and highly pipelined architecture resulting in high-speed performance, which cannot be matched by DSPs. However, wh… text/html 2010-12-24T10:35:19+00:00 http://www.ee.iitm.ac.in/vlsi/people/srini/project/p10?rev=1293186919&do=diff Hardware implementation of video imaging system for launch vehicles. The project is a hardware implementation for obtaining compressed, good quality image capture of the GSLV/PSLV launch vehicle, especially during stage separation. This requires high performance hardware such as FPGA or ASIC to cope with the requirements of high speed, moderate compression and good quality. Hence, FPGA based implementation of the video codec (encoder/decoder) has been undertaken. At the encoder end, data acquir…